summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2013-04-03 09:55:22 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-04-03 19:26:05 +0200
commit23f50166c64be0c1d3656ca67839843bf11a5274 (patch)
treed75c407b2e432303ea068a98c65c4d2be93873fe /src/cpu/intel
parent13cc952a13ea29d9c5016a861d97da8326c87c4e (diff)
downloadcoreboot-23f50166c64be0c1d3656ca67839843bf11a5274.tar.xz
haswell: enable ROM caching
If ROM caching is selected the haswell CPU initialization code will enable ROM caching after all other CPU threads are brought up. Change-Id: I75424bb75174bfeca001468c3272e6375e925122 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/haswell_init.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 0bb11a8ed0..18636b0840 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -551,6 +551,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
/* After SMM relocation a 2nd microcode load is required. */
intel_microcode_load_unlocked(microcode_patch);
+
+ /* Enable ROM caching if option was selected. */
+ x86_mtrr_enable_rom_caching();
}
static struct device_operations cpu_dev_ops = {