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authorAaron Durbin <adurbin@chromium.org>2015-06-09 13:55:51 -0500
committerAaron Durbin <adurbin@chromium.org>2015-06-09 22:06:40 +0200
commit42e6856436e6ee1f9b8ae1039ac5a0921e001377 (patch)
tree3a9d4dc8c13154aa92436d6a24a170ead884f4ce /src/cpu/intel
parent41607a4682c75b716e342cfc773926c753fb6086 (diff)
downloadcoreboot-42e6856436e6ee1f9b8ae1039ac5a0921e001377.tar.xz
stage_cache: use cbmem init hooks
Instead of having the chipset code make the approrpiate calls at the appropriate places use the cbmem init hooks to take the appropriate action. That way no chipset code needs to be changed in order to support the external stage cache. Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/romstage.c15
1 files changed, 5 insertions, 10 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 0f0890a104..6adb8be9ce 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -35,7 +35,6 @@
#include <cbfs.h>
#include <romstage_handoff.h>
#include <reset.h>
-#include <stage_cache.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include <ec/google/chromeec/ec.h>
@@ -256,17 +255,13 @@ void romstage_common(const struct romstage_params *params)
if (!wake_from_s3) {
cbmem_initialize_empty();
- stage_cache_create_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
- } else {
- stage_cache_recover();
- if (cbmem_initialize()) {
- #if CONFIG_HAVE_ACPI_RESUME
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
- #endif
- }
+ } else if (cbmem_initialize()) {
+ #if CONFIG_HAVE_ACPI_RESUME
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
+ #endif
}
handoff = romstage_handoff_find_or_add();