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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2011-04-11 20:17:22 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-11 20:17:22 +0000
commit5005bb06c17461ef75cd1fef55c24dffaa05e580 (patch)
tree2c38986a89152225ad56cb44227f5bc6ddbecd06 /src/cpu/intel
parent1fa61ebb3344105ae633ed7eb1be05cc574b666c (diff)
downloadcoreboot-5005bb06c17461ef75cd1fef55c24dffaa05e580.tar.xz
Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc5
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram.inc5
4 files changed, 12 insertions, 8 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 99c159977e..3949a567c8 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -24,6 +24,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
+#include <cpu/x86/post_code.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
@@ -364,7 +365,7 @@ lout:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -375,7 +376,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index d7dba8bf1b..e9820c9aeb 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index b077ff9a48..fc4947600f 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 3737429325..a1b82675fb 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -243,7 +244,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@@ -254,7 +255,7 @@ __main:
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt