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authorArthur Heymans <arthur@aheymans.xyz>2018-06-12 22:58:19 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-21 15:50:16 +0000
commit58a89537931cd243c6ddbb9ff435bc5862fc64b0 (patch)
tree513a5a682063919f1f6c99d638ba75e6fbc86c3a /src/cpu/intel
parent4dfb5f1055b03d27a509272e1a68de45c3fa2266 (diff)
downloadcoreboot-58a89537931cd243c6ddbb9ff435bc5862fc64b0.tar.xz
Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_2065x/bootblock.c1
-rw-r--r--src/cpu/intel/model_206ax/bootblock.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index edc2996f05..ed528d1bdd 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -24,7 +24,6 @@
#include <cpu/intel/microcode/microcode.c>
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
-#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 90215a496d..670b09750e 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -28,7 +28,6 @@
IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/rcba.h>
#else
#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif