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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-27 11:27:56 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-29 07:32:43 +0200
commit65e8f647bc55ee28bd389789788e666279537510 (patch)
treee93254e6c05cebec7beaf698437bb576aae656b6 /src/cpu/intel
parent7b3512dde3efa3d25d715bb61326ebfc995e9a69 (diff)
downloadcoreboot-65e8f647bc55ee28bd389789788e666279537510.tar.xz
intel romstage: Use run_ramstage()
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 11d449c1ae..9cd4ae009d 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -26,10 +26,10 @@
#include <timestamp.h>
#include <arch/acpi.h>
#include <arch/io.h>
-#include <arch/stages.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
+#include <program_loading.h>
#include <romstage_handoff.h>
#include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -283,7 +283,7 @@ void romstage_after_car(void)
acpi_prepare_for_resume();
/* Load the ramstage. */
- copy_and_run();
+ run_ramstage();
}