summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2013-05-01 15:39:28 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-05-07 18:32:41 +0200
commit7cb1ba9a61b244800eb65c08729f75d85a504de3 (patch)
treed18c0a0964ebc7b92ddc443774055da043dd7a52 /src/cpu/intel
parent935850e08293cec1cb27d12358b27285e780566a (diff)
downloadcoreboot-7cb1ba9a61b244800eb65c08729f75d85a504de3.tar.xz
haswell: use tsc for udelay()
Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3169 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/Kconfig3
-rw-r--r--src/cpu/intel/haswell/Makefile.inc3
-rw-r--r--src/cpu/intel/haswell/tsc_freq.c31
3 files changed, 36 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 13861f9185..152059fcbe 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS
def_bool y
select SMP
select SSE2
- select UDELAY_LAPIC
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
select SMM_TSEG
select SMM_MODULES
select RELOCATABLE_MODULES
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 90ffd66699..60c061ddd7 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -1,7 +1,9 @@
ramstage-y += haswell_init.c
subdirs-y += ../../x86/name
ramstage-y += mp_init.c
+ramstage-y += tsc_freq.c
romstage-y += romstage.c
+romstage-y += tsc_freq.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
@@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
diff --git a/src/cpu/intel/haswell/tsc_freq.c b/src/cpu/intel/haswell/tsc_freq.c
new file mode 100644
index 0000000000..0a7805319d
--- /dev/null
+++ b/src/cpu/intel/haswell/tsc_freq.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include "cpu/intel/haswell/haswell.h"
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t platform_info;
+
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+ return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff);
+}