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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-27 13:24:11 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-11 18:43:10 +0100
commita4ffe9dda0eb50eb698fef303f426408338fa0ff (patch)
treee8e7026a1cc0c3e5e3929e47905015da524e3011 /src/cpu/intel
parent9b9915284f5070c6f664fa36495ae831e95ea819 (diff)
downloadcoreboot-a4ffe9dda0eb50eb698fef303f426408338fa0ff.tar.xz
intel post-car: Separate files for setup_stack_and_mtrrs()
Have a common romstage.c file to prepare CAR stack guards. MTRR setup around cbmem_top() is somewhat northbridge specific, place stubs under northbridge for platrform that will move to RELOCATABLE_RAMSTAGE. Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15762 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/car/romstage.c51
1 files changed, 50 insertions, 1 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c6df446c6a..d04b6e120c 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -1,7 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <program_loading.h>
+
+#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x800
void * asmlinkage romstage_main(unsigned long bist)
{
+ int i;
+ void *romstage_stack_after_car;
+ const int num_guards = 4;
+ const u32 stack_guard = 0xdeadbeef;
+ u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
+ CONFIG_DCACHE_RAM_SIZE -
+ DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+
+ for (i = 0; i < num_guards; i++)
+ stack_base[i] = stack_guard;
+
mainboard_romstage_entry(bist);
- return (void*)CONFIG_RAMTOP;
+
+ /* Check the stack. */
+ for (i = 0; i < num_guards; i++) {
+ if (stack_base[i] == stack_guard)
+ continue;
+ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
+ }
+
+ /* Get the stack to use after cache-as-ram is torn down. */
+ if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
+ romstage_stack_after_car = (void*)CONFIG_RAMTOP;
+ else
+ romstage_stack_after_car = setup_stack_and_mtrrs();
+
+ return romstage_stack_after_car;
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ /* Load the ramstage. */
+ run_ramstage();
}