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authorPatrick Georgi <pgeorgi@chromium.org>2015-05-19 21:30:20 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-05-19 22:08:32 +0200
commita6b4798ac00a72a5bab16605a1fdb9d2ffcffd71 (patch)
treeb0cc9f76c23e67f003e95c1ad0fd10c8ca07fa75 /src/cpu/intel
parente2b0affd6c36d332aaf31e9438a9be048943d611 (diff)
downloadcoreboot-a6b4798ac00a72a5bab16605a1fdb9d2ffcffd71.tar.xz
intel/haswell: Drop MONOTONIC_TIMER_MSR
The variable was set on all haswell boards, so we can do it like on broadwell where the MSR based timer is assumed to be around, too. Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10256 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/Kconfig8
-rw-r--r--src/cpu/intel/haswell/Makefile.inc4
2 files changed, 3 insertions, 9 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 00fb1d7c57..f2848078f3 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select BACKUP_DEFAULT_SMM_REGION
+ select HAVE_MONOTONIC_TIMER
select SMP
select MMX
select SSE
@@ -60,11 +61,4 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
the system will reset otherwise the ramstage will be reloaded from
cbfs.
-config MONOTONIC_TIMER_MSR
- def_bool n
- depends on INTEL_LYNXPOINT_LP
- select HAVE_MONOTONIC_TIMER
- help
- Provide a monotonic timer using the 24MHz MSR counter.
-
endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 57f9120d5a..4297122e69 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -6,7 +6,7 @@ romstage-y += tsc_freq.c
ramstage-y += acpi.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
-ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
+ramstage-y += monotonic_timer.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
@@ -14,7 +14,7 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
-smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
+smm-y += monotonic_timer.c
cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc