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authorAaron Durbin <adurbin@chromium.org>2013-03-13 13:51:20 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-22 00:13:56 +0100
commitc0cbd6e8c2bad5453f7c3b6961bc12d03862497a (patch)
tree0555d58b3ff09a5cc1eb7435b973e3d75a0095cb /src/cpu/intel
parentdd4a6d2357decf0cf505370234b378985c68f97f (diff)
downloadcoreboot-c0cbd6e8c2bad5453f7c3b6961bc12d03862497a.tar.xz
haswell: use dynamic cbmem
Convert the existing haswell code to support reloctable ramstage to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as this option is a hard requirement for relocatable ramstage. Aside from converting a few new API calls, a cbmem_top() implementation is added which is defined to be at the begining of the TSEG region. Also, use the dynamic cbmem library for allocating a stack in ram for romstage after CAR is torn down. Utilizing dynamic cbmem does mean that the cmem field in the gnvs chromeos acpi table is now 0. Also, the memconsole driver in the kernel won't be able to find the memconsole because the cbmem structure changed. Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2850 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/Kconfig1
-rw-r--r--src/cpu/intel/haswell/romstage.c49
2 files changed, 23 insertions, 27 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index d1f521d69f..5f27d4c7e1 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SMM_TSEG
select SMM_MODULES
select RELOCATABLE_MODULES
+ select DYNAMIC_CBMEM
select CPU_MICROCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 6164de54ed..5dc45010d7 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -32,7 +32,6 @@
#include <arch/stages.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
-#include <cbmem.h>
#include <cbfs.h>
#include <romstage_handoff.h>
#include <reset.h>
@@ -70,13 +69,17 @@ static inline u32 *stack_push(u32 *stack, u32 value)
return stack;
}
+/* Romstage needs quite a bit of stack for decompressing images since the lzma
+ * lib keeps its state on the stack during romstage. */
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
static unsigned long choose_top_of_stack(void)
{
unsigned long stack_top;
-#if CONFIG_RELOCATABLE_RAMSTAGE
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_RESUME_SCRATCH,
- CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
- stack_top += CONFIG_HIGH_SCRATCH_MEMORY_SIZE;
+#if CONFIG_DYNAMIC_CBMEM
+ /* cbmem_add() does a find() before add(). */
+ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
+ ROMSTAGE_RAM_STACK_SIZE);
+ stack_top += ROMSTAGE_RAM_STACK_SIZE;
#else
stack_top = ROMSTAGE_STACK;
#endif
@@ -197,7 +200,6 @@ void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
- int cbmem_was_initted;
struct romstage_handoff *handoff;
#if CONFIG_COLLECT_TIMESTAMPS
@@ -265,23 +267,16 @@ void romstage_common(const struct romstage_params *params)
quick_ram_check();
post_code(0x3e);
-#if CONFIG_EARLY_CBMEM_INIT
- cbmem_was_initted = !cbmem_initialize();
-#else
- cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
- - HIGH_MEMORY_SIZE));
-#endif
-
- /* Save data returned from MRC on non-S3 resumes. */
- if (!wake_from_s3)
+ if (!wake_from_s3) {
+ cbmem_initialize_empty();
+ /* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
-
-#if CONFIG_HAVE_ACPI_RESUME
- if (wake_from_s3 && !cbmem_was_initted) {
+ } else if (cbmem_initialize()) {
+ #if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
+ #endif
}
-#endif
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
@@ -330,11 +325,16 @@ void romstage_after_car(void)
#if CONFIG_RELOCATABLE_RAMSTAGE
void cache_loaded_ramstage(struct romstage_handoff *handoff,
- void *ramstage_base, uint32_t ramstage_size,
+ const struct cbmem_entry *ramstage,
void *entry_point)
{
struct ramstage_cache *cache;
uint32_t total_size;
+ uint32_t ramstage_size;
+ void *ramstage_base;
+
+ ramstage_size = cbmem_entry_size(ramstage);
+ ramstage_base = cbmem_entry_start(ramstage);
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of ram is defined to be the TSEG base address. */
@@ -358,19 +358,14 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff,
/* Copy over the program. */
memcpy(&cache->program[0], ramstage_base, ramstage_size);
- /* Do not update reserve region if the handoff structure is not
- * available. Perhaps the ramstage will fix things up for the resume
- * path. */
if (handoff == NULL)
return;
- /* Update entry and reserve region. */
- handoff->reserve_base = (uint32_t)ramstage_base;
- handoff->reserve_size = ramstage_size;
handoff->ramstage_entry_point = (uint32_t)entry_point;
}
-void *load_cached_ramstage(struct romstage_handoff *handoff)
+void *load_cached_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage)
{
struct ramstage_cache *cache;