summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-08-06 12:10:10 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-08-09 08:49:19 +0000
commitcb5304bc0a64b7d7235e3d48abdb8a4cf499c3a8 (patch)
tree3767f562a3e6fee0df5d7e159d7618664e006d96 /src/cpu/intel
parent60828b7fa9ad888aee0c7dfff17b5b6a507f2469 (diff)
downloadcoreboot-cb5304bc0a64b7d7235e3d48abdb8a4cf499c3a8.tar.xz
cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c34
1 files changed, 20 insertions, 14 deletions
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index b48fe006bc..cf68ecf4c2 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -160,20 +160,26 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
- /* SMRR has 32-bits of valid address aligned to 4KiB. */
- struct cpuinfo_x86 c;
-
- /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
- get_fms(&c, cpuid_eax(1));
- if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
- params->smrr_base.lo = (params->smram_base & rmask);
- else
- params->smrr_base.lo = (params->smram_base & rmask)
- | MTRR_TYPE_WRBACK;
- params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
- | MTRR_PHYS_MASK_VALID;
- params->smrr_mask.hi = 0;
+ if (IS_ALIGNED(tsegmb, tseg_size)) {
+ /* SMRR has 32-bits of valid address aligned to 4KiB. */
+ struct cpuinfo_x86 c;
+
+ /* On model_6fx and model_1067x bits [0:11] on smrr_base
+ are reserved */
+ get_fms(&c, cpuid_eax(1));
+ if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
+ params->smrr_base.lo = (params->smram_base & rmask);
+ else
+ params->smrr_base.lo = (params->smram_base & rmask)
+ | MTRR_TYPE_WRBACK;
+ params->smrr_base.hi = 0;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
+ params->smrr_mask.hi = 0;
+ } else {
+ printk(BIOS_WARNING,
+ "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+ }
}
static int install_relocation_handler(int *apic_id_map, int num_cpus,