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authorAaron Durbin <adurbin@chromium.org>2012-12-11 17:15:13 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 05:10:32 +0100
commitdc278f8fd0318caf0c11330478dff8453bb1107d (patch)
treea7806a62b78a1915cf9838f2a5a144c89c9d8faf /src/cpu/intel
parentc1989c494e2628618067d03d9e192ac25b4f42d1 (diff)
downloadcoreboot-dc278f8fd0318caf0c11330478dff8453bb1107d.tar.xz
haswell: Properly Guard Engergy Policy by CPUID
The IA32_ENERGY_PERFORMANCE_BIAS MSR can only be read or written to if the CPU supports it. The support is indicated by ECX[3] for cpuid(6). Without this guard, some Haswell parts would GP# fault in this routine. No more GP# while running on haswell CRBs. Change-Id: If41e1e133e5faebb3ed578cba60743ce7e1c196f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2639 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/haswell_init.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 01d151ee06..9984c55d95 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -404,6 +404,12 @@ static void set_max_ratio(void)
static void set_energy_perf_bias(u8 policy)
{
msr_t msr;
+ int ecx;
+
+ /* Determine if energy efficient policy is supported. */
+ ecx = cpuid_ecx(0x6);
+ if (!(ecx & (1 << 3)))
+ return;
/* Energy Policy is bits 3:0 */
msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);