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authorMartin Roth <martinroth@google.com>2015-08-18 10:41:54 -0600
committerMartin Roth <martinroth@google.com>2015-08-25 17:36:45 +0000
commitdf205067c976d917563a02fc6ebf1cff329a4097 (patch)
tree325c4cf09361bada19aee32c8fdf009aabd4e641 /src/cpu/intel
parent1fff0d26f80c9f412a500f40b29bbbd88572febc (diff)
downloadcoreboot-df205067c976d917563a02fc6ebf1cff329a4097.tar.xz
Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/socket_rPGA988B/Kconfig4
-rw-r--r--src/cpu/intel/socket_rPGA989/Kconfig4
4 files changed, 0 insertions, 16 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 0a070b2e81..0978bfb0ac 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -151,7 +151,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -161,7 +160,6 @@ clear_mtrrs:
movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -219,7 +217,6 @@ before_romstage:
andl $~1, %eax
wrmsr
-#if CONFIG_CACHE_MRC_BIN
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
@@ -227,7 +224,6 @@ before_romstage:
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
wrmsr
-#endif
post_code(0x33)
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 2d469ffa03..a3f1c649c1 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -146,7 +146,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
/* Enable caching for ram init code to run faster */
movl $MTRRphysBase_MSR(2), %ecx
movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -156,7 +155,6 @@ clear_mtrrs:
movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -211,7 +209,6 @@ before_romstage:
andl $~1, %eax
wrmsr
-#if CONFIG_CACHE_MRC_BIN
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
@@ -219,7 +216,6 @@ before_romstage:
wrmsr
movl $MTRRphysMask_MSR(2), %ecx
wrmsr
-#endif
post_code(0x33)
diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig
index 471e5220cf..753cfb30c9 100644
--- a/src/cpu/intel/socket_rPGA988B/Kconfig
+++ b/src/cpu/intel/socket_rPGA988B/Kconfig
@@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX
select SSE
-config CACHE_MRC_BIN
- bool
- default n
-
endif
diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
index 83d29e7d23..1d1f64fdbd 100644
--- a/src/cpu/intel/socket_rPGA989/Kconfig
+++ b/src/cpu/intel/socket_rPGA989/Kconfig
@@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX
select SSE
-config CACHE_MRC_BIN
- bool
- default n
-
endif