summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-07-20 23:31:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-24 18:34:37 +0000
commite750b38e4834867ec362b59f150ef6ae9fe888c6 (patch)
treefa85e7241ca2496c45e103a2a2c62ce053b473cc /src/cpu/intel
parent6b27c38f4afdd7b20100c4a772fa4077ae437cf1 (diff)
downloadcoreboot-e750b38e4834867ec362b59f150ef6ae9fe888c6.tar.xz
cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/smmrelocate.c4
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 9ff1e55c81..56ee47bc97 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -70,8 +70,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_emrr(struct smm_relocation_params *relo_params)
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index e80fa31489..9806882376 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -61,8 +61,8 @@ static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
/* The relocation work is actually performed in SMM context, but the code