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authorJon Dufresne <jon.dufresne@gmail.com>2006-12-14 00:40:09 +0000
committerStefan Reinauer <stepan@openbios.org>2006-12-14 00:40:09 +0000
commita522df039b3085004dbff39fec675039d57b1fab (patch)
tree0ea9d737f090cce9e1aa1d959058c5b8841c47af /src/cpu/intel
parent0fac1e56d70b048309d0406a92b8bf2e8253ca78 (diff)
downloadcoreboot-a522df039b3085004dbff39fec675039d57b1fab.tar.xz
Add mtrr support for pentium m cpus
For cache to work the x86_setup_mtrrs() must be called. Closes #61 Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_69x/model_69x_init.c1
-rw-r--r--src/cpu/intel/model_6dx/model_6dx_init.c1
-rw-r--r--src/cpu/intel/model_6xx/model_6xx_init.c1
3 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index 600ad46418..9ea49a9c55 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -24,6 +24,7 @@ static void model_69x_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index ca00df43b4..3214bdd4bd 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -24,6 +24,7 @@ static void model_6dx_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 70010a32fa..cf0383f46a 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -30,6 +30,7 @@ static void model_6xx_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
+ x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */