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| author | Li-Ta Lo <ollie@lanl.gov> | 2004-03-23 21:28:05 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-03-23 21:28:05 +0000 |
| commit | e52666931a3e34895b3f3b92641de9774ab722ec (patch) | |
| tree | 890bb66a0a16ec7a57230283f000ee91eeb0b384 /src/cpu/k8 | |
| parent | 9f46132e9627d24f3ad76619cf3340006a4012fb (diff) | |
| download | coreboot-e52666931a3e34895b3f3b92641de9774ab722ec.tar.xz | |
Doxidization, reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/k8')
| -rw-r--r-- | src/cpu/k8/Config.lb | 3 | ||||
| -rw-r--r-- | src/cpu/k8/cpufixup.c | 2 | ||||
| -rw-r--r-- | src/cpu/k8/earlymtrr.c | 13 | ||||
| -rw-r--r-- | src/cpu/k8/earlymtrr.inc | 19 |
4 files changed, 33 insertions, 4 deletions
diff --git a/src/cpu/k8/Config.lb b/src/cpu/k8/Config.lb index a0a702e043..9081b07714 100644 --- a/src/cpu/k8/Config.lb +++ b/src/cpu/k8/Config.lb @@ -1,3 +1,6 @@ +# How does the config tool pick the correct +# cpufixup.c to generate cupfixup.o ? + uses k8 uses CPU_FIXUP default k8=1 diff --git a/src/cpu/k8/cpufixup.c b/src/cpu/k8/cpufixup.c index 2d347de829..c25a473d2e 100644 --- a/src/cpu/k8/cpufixup.c +++ b/src/cpu/k8/cpufixup.c @@ -428,5 +428,5 @@ void k8_enable(struct chip *chip, enum chip_pass pass) struct chip_control cpu_k8_control = { .enable = k8_enable, - .name = "AMD K8", + .name = "AMD K8 CPU", }; diff --git a/src/cpu/k8/earlymtrr.c b/src/cpu/k8/earlymtrr.c index 5fb63d2e7d..2138e3fefe 100644 --- a/src/cpu/k8/earlymtrr.c +++ b/src/cpu/k8/earlymtrr.c @@ -27,13 +27,24 @@ static void early_mtrr_init(void) msr_t msr; const unsigned long *msr_addr; + /* Enable the access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(msr); + /* Inialize all of the relevant msrs to 0 */ msr.lo = 0; msr.hi = 0; - for(msr_addr = mtrr_msrs; *msr_addr; msr_addr++) { + + for (msr_addr = mtrr_msrs; *msr_addr; msr_addr++) { wrmsr(*msr_addr, msr); } + /* Disable the access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(msr); + /* Enable memory access for 0 - 1MB using top_mem */ msr.hi = 0; msr.lo = ((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK; diff --git a/src/cpu/k8/earlymtrr.inc b/src/cpu/k8/earlymtrr.inc index acc917be7d..6f8537d255 100644 --- a/src/cpu/k8/earlymtrr.inc +++ b/src/cpu/k8/earlymtrr.inc @@ -13,6 +13,13 @@ earlymtrr_start: xorl %edx, %edx # movl $fixed_mtrr_msr, %esi +enable_fixed_mtrr_dram_modify: + /* Enable the access to AMD RdDram and WrDram extension bits */ + movl $SYSCFG_MSR, %ecx + rdmsr + orl $SYSCFG_MSR_MtrrFixDramModEn, %eax + wrmsr + clear_fixed_var_mtrr: lodsl (%esi), %eax testl %eax, %eax @@ -25,7 +32,14 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -/* enable memory access for 0 - 1MB using top_mem */ +disable_fixed_mtrr_dram_modify: + /* Disable the access to AMD RdDram and WrDram extension bits */ + movl $SYSCFG_MSR, %ecx + rdmsr + andl $(~SYSCFG_MSR_MtrrFixDramModEn), %eax + wrmsr + + /* enable memory access for 0 - 1MB using top_mem */ movl $TOP_MEM, %ecx xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax @@ -72,9 +86,10 @@ enable_mtrr: movl $0x00000800, %eax wrmsr - /* Enable the MTRRs in SYSCFG */ + /* Enable the MTRRs and IORRs in SYSCFG */ movl $SYSCFG_MSR, %ecx rdmsr + /* Don't enable SYSCFG_MSR_MtrrFixDramEn) untill we have done with VGA BIOS */ orl $(SYSCFG_MSR_MtrrVarDramEn), %eax wrmsr |