diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2008-01-18 15:08:58 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2008-01-18 15:08:58 +0000 |
| commit | f8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch) | |
| tree | 7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/cpu/ppc/mpc74xx | |
| parent | 7e61e45402aba2b90997f4f02ca8266cf65a229a (diff) | |
| download | coreboot-f8ee1806ac524bc782c93eccc59ee3c929abddb9.tar.xz | |
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc/mpc74xx')
| -rw-r--r-- | src/cpu/ppc/mpc74xx/Config.lb | 2 | ||||
| -rw-r--r-- | src/cpu/ppc/mpc74xx/mpc74xx.inc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb index 8665fa35c0..ee65e41f3b 100644 --- a/src/cpu/ppc/mpc74xx/Config.lb +++ b/src/cpu/ppc/mpc74xx/Config.lb @@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE ## Use cache ram for initial setup ## default USE_DCACHE_RAM=1 -## Set dcache ram above linuxbios image +## Set dcache ram above coreboot image default DCACHE_RAM_BASE=_RAMBASE+0x100000 ## Dcache size is 32Kb default DCACHE_RAM_SIZE=0x8000 diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc index aa55df8789..ba2c0018d5 100644 --- a/src/cpu/ppc/mpc74xx/mpc74xx.inc +++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc @@ -19,7 +19,7 @@ /* * The aim of this code is to bring the machine from power-on to the point - * where we can jump to the the main LinuxBIOS entry point hardwaremain() + * where we can jump to the the main coreboot entry point hardwaremain() * which is written in C. * * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing @@ -79,7 +79,7 @@ isync /* - * Clear segment registers (LinuxBIOS doesn't use these) + * Clear segment registers (coreboot doesn't use these) */ mtsr 0, r0 isync |