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| author | Greg Watson <gwatson@lanl.gov> | 2005-10-19 18:03:08 +0000 |
|---|---|---|
| committer | Greg Watson <gwatson@lanl.gov> | 2005-10-19 18:03:08 +0000 |
| commit | 58b971e79978448890f8afe688c849bf88f59afc (patch) | |
| tree | 4162fc4299af3c70f0b1faa4b5d518ea7fcb8265 /src/cpu/ppc/ppc970/Config.lb | |
| parent | 1cf26a88841765e7b9477e922199476a92ac4fa4 (diff) | |
| download | coreboot-58b971e79978448890f8afe688c849bf88f59afc.tar.xz | |
start of 970 port
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc/ppc970/Config.lb')
| -rw-r--r-- | src/cpu/ppc/ppc970/Config.lb | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/cpu/ppc/ppc970/Config.lb b/src/cpu/ppc/ppc970/Config.lb new file mode 100644 index 0000000000..3b430e27cb --- /dev/null +++ b/src/cpu/ppc/ppc970/Config.lb @@ -0,0 +1,19 @@ +## +## CPU initialization +## +uses _RAMBASE +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE + +## +## Use cache ram for initial setup +## +default USE_DCACHE_RAM=1 +## Set dcache ram above linuxbios image +default DCACHE_RAM_BASE=_RAMBASE+0x100000 +## Dcache size is 32Kb +default DCACHE_RAM_SIZE=0x8000 + +initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc + |