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authorGreg Watson <jarrah@users.sourceforge.net>2004-04-21 22:26:08 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-04-21 22:26:08 +0000
commit12c3154cee6b0c8167d4bf704c5ca25291c7ef71 (patch)
tree34d43ec89fc4b8f2d43f5e710e4a776a7cad3fa9 /src/cpu/ppc
parentbe167e79cf23bfc530c6973a7879a2451c28e422 (diff)
downloadcoreboot-12c3154cee6b0c8167d4bf704c5ca25291c7ef71.tar.xz
moved to crt0.S.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc')
-rw-r--r--src/cpu/ppc/mpc74xx/mpc74xx.inc12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index 55e290dbe9..d99ec6a247 100644
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -172,15 +172,3 @@
ori r2, r2, HID0_DCE | HID0_DCFI
sync
mtspr HID0, r2
-
- /*
- * Initialize data cache blocks
- * (assumes cache block size of 32 bytes)
- */
- lis r1, DCACHE_RAM_BASE@h
- ori r1, r1, DCACHE_RAM_BASE@l
- li r3, (DCACHE_RAM_SIZE / 32)
- mtctr r3
-0: dcbz r0, r1
- addi r1, r1, 32
- bdnz 0b