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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-10-05 05:12:56 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-10-05 05:12:56 +0000 |
| commit | ccf4d34bb746356486d4c02599d9e5c8346b8d81 (patch) | |
| tree | 0ec239a5e332c733825408442e5e377bea8449d5 /src/cpu/ppc | |
| parent | 95ae7c1e5cb57e6fb69fab163ad68acfed83c320 (diff) | |
| download | coreboot-ccf4d34bb746356486d4c02599d9e5c8346b8d81.tar.xz | |
use standard name
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/ppc/ppc4xx/clock.c b/src/cpu/ppc/ppc4xx/clock.c index 770c0fa117..01914e0752 100644 --- a/src/cpu/ppc/ppc4xx/clock.c +++ b/src/cpu/ppc/ppc4xx/clock.c @@ -44,12 +44,12 @@ void get_sys_info (struct ppc4xx_sys_info * sysInfo) /* * Read PLL Mode register */ - pllmr = ppc_getdcr(CPC0_PLLMR); + pllmr = mfdcr(CPC0_PLLMR); /* * Read Pin Strapping register */ - psr = ppc_getdcr(CPC0_PSR); + psr = mfdcr(CPC0_PSR); /* * Determine FWD_DIV. |