add .h files for common exynos 5

Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1926
Tested-by: build bot (Jenkins)

1 files changed, 71 insertions, 0 deletions

diff --git a/src/cpu/samsung/exynos5-common/clk.h b/src/cpu/samsung/exynos5-common/clk.h
new file mode 100644
index 0000000000..0178f88ff2
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/clk.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2012 The Chromium Authors
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __EXYNOS_COMMON_CLK_H_
+#define __EXYNOS_COMMON_CLK_H_
+
+#include <types.h>
+#include <stdint.h>
+
+enum periph_id;
+
+#define APLL	0
+#define MPLL	1
+#define EPLL	2
+#define HPLL	3
+#define VPLL	4
+#define BPLL	5
+
+enum pll_src_bit {
+	SRC_MPLL = 6,
+	SRC_EPLL,
+	SRC_VPLL,
+};
+
+/* *
+ * This structure is to store the src bit, div bit and prediv bit
+ * positions of the peripheral clocks of the src and div registers
+ */
+struct clk_bit_info {
+	s8 src_bit;    /* offset in register to clock source field */
+	s8 n_src_bits; /* number of bits in 'src_bit' field */
+	s8 div_bit;
+	s8 prediv_bit;
+};
+
+/* FIXME(dhendrix) conflicts with stp-common/clk.h */
+#if 0
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+void set_mmc_clk(int dev_index, unsigned int div);
+#endif
+
+/**
+ * get the clk frequency of the required peripherial
+ *
+ * @param peripherial	Peripherial id
+ *
+ * @return frequency of the peripherial clk
+ */
+unsigned long clock_get_periph_rate(enum periph_id peripheral);
+
+#endif