Exynos5250: Get DDR3 working by changing what is compiled and add a function

This is a minor set of changes to get DDR3 going.

Move compilation of DDR3 startup to the romstage. Fix a prototype that
was missing a void. Remove a function that is overly flexible, and
even though it is overly flexible only actually can handle one type of
RAM. Mainboards only support one type of DRAM, so create a function
to explicitly initialize the type of DDR we have -- DDR3.

With these changes, and the previous changes, google snow is ready to run
the ramstage.

Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 1b915a3266..6eee50328f 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -11,6 +11,8 @@ romstage-y += pinmux.c
 romstage-y += power.c
 romstage-y += soc.c
 romstage-y += uart.c
+romstage-y += dmc_common.c
+romstage-y += dmc_init_ddr3.c
 
 #ramstage-y += clock.c
 #ramstage-y += clock_init.c
@@ -30,8 +32,6 @@ ramstage-y += uart.c
 #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
 #ramstage-$(CONFIG_SATA_AHCI) += sata.c
 ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c
-ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c
-ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c
 
 exynos5250_add_bl1: $(obj)/coreboot.pre
 	printf "    DD         Adding Samsung Exynos5250 BL1\n"