diff options
author | David Hendricks <dhendrix@chromium.org> | 2013-03-28 19:04:58 -0700 |
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committer | David Hendricks <dhendrix@chromium.org> | 2013-03-29 22:24:31 +0100 |
commit | c01d1380138e807fa941976d9f102fb1b200ad01 (patch) | |
tree | e625be73581cc2c84bea28041ec7cd887ea326b0 /src/cpu/samsung/exynos5250/Makefile.inc | |
parent | bae3f062457cf52da8e06e6abebfb99084411646 (diff) | |
download | coreboot-c01d1380138e807fa941976d9f102fb1b200ad01.tar.xz |
exynos5250: Add function for configuring L2 cache
This adds a new function to configure L2 cache for the
exynos5250 and deprecates the old function.
Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2949
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/samsung/exynos5250/Makefile.inc')
-rw-r--r-- | src/cpu/samsung/exynos5250/Makefile.inc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 961b719505..74bc871f36 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,12 +9,10 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c -bootblock-y += exynos_cache.c romstage-y += clock.c romstage-y += clock_init.c romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. -romstage-y += exynos_cache.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c @@ -24,7 +22,6 @@ romstage-$(CONFIG_EARLY_CONSOLE) += uart.c #ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c -ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c |