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author | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-29 14:35:35 -0800 |
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committer | David Hendricks <dhendrix@chromium.org> | 2013-01-30 21:39:22 +0100 |
commit | b7e05358621344e0d777853c34960944d680f804 (patch) | |
tree | 1735417d681ed532639120626598d63e902c00c0 /src/cpu/samsung/exynos5250/clock_init.c | |
parent | 21d0fc0d3701d1c359fb4d4267383aeaa5886a7e (diff) | |
download | coreboot-b7e05358621344e0d777853c34960944d680f804.tar.xz |
Exynos5250: Get DDR3 working by changing what is compiled and add a function
This is a minor set of changes to get DDR3 going.
Move compilation of DDR3 startup to the romstage. Fix a prototype that
was missing a void. Remove a function that is overly flexible, and
even though it is overly flexible only actually can handle one type of
RAM. Mainboards only support one type of DRAM, so create a function
to explicitly initialize the type of DDR we have -- DDR3.
With these changes, and the previous changes, google snow is ready to run
the ramstage.
Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/cpu/samsung/exynos5250/clock_init.c')
-rw-r--r-- | src/cpu/samsung/exynos5250/clock_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index ea91bb4355..565abe1efb 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -744,7 +744,7 @@ struct mem_timings *clock_get_mem_timings(void) return NULL; } -void system_clock_init() +void system_clock_init(void) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = |