diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-03-28 19:04:58 -0700 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2013-03-29 22:24:31 +0100 |
| commit | c01d1380138e807fa941976d9f102fb1b200ad01 (patch) | |
| tree | e625be73581cc2c84bea28041ec7cd887ea326b0 /src/cpu/samsung/exynos5250/cpu.c | |
| parent | bae3f062457cf52da8e06e6abebfb99084411646 (diff) | |
| download | coreboot-c01d1380138e807fa941976d9f102fb1b200ad01.tar.xz | |
exynos5250: Add function for configuring L2 cache
This adds a new function to configure L2 cache for the
exynos5250 and deprecates the old function.
Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2949
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/samsung/exynos5250/cpu.c')
| -rw-r--r-- | src/cpu/samsung/exynos5250/cpu.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index b6eae46a81..4bb06e8b4a 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/cache.h> +#include <cpu/samsung/exynos5250/cpu.h> #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -33,3 +35,17 @@ struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") .enable_dev = enable_dev, }; + +void exynos5250_config_l2_cache(void) +{ + uint32_t val; + + /* + * Bit 9 - L2 tag RAM setup (1 cycle) + * Bits 8:6 - L2 tag RAM latency (3 cycles) + * Bit 5 - L2 data RAM setup (1 cycle) + * Bits 2:0 - L2 data RAM latency (3 cycles) + */ + val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); + write_l2ctlr(val); +} |