exynos5420: add a peripheral clock select --> PLL decoder

This adds a helper function to translate between peripheral clock
select fields in clock source registers and PLLs. Some of this was
already done to handle a few special cases, this generalizes the
earlier work so that follow-up patches can do further clean-up.

Unfortunately, the PLLs represented by clock select fields in
various modules are not uniformly ordered. So for now we focus on
peripheral clock sources only.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff
Reviewed-on: https://gerrit.chromium.org/gerrit/65283
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4462
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 2 insertions, 10 deletions

diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index b37c076582..c5e7f589ba 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -25,6 +25,7 @@
 
 enum periph_id;
 
+/* This master list of PLLs is ordered arbitrarily. */
 #define APLL	0
 #define MPLL	1
 #define EPLL	2
@@ -35,16 +36,7 @@ enum periph_id;
 #define SPLL	7
 #define CPLL	8
 #define DPLL	9
-
-enum pll_src_bit {
-	EXYNOS_SRC_CPLL = 1,
-	EXYNOS_SRC_DPLL = 2,
-	EXYNOS_SRC_MPLL = 3,
-	EXYNOS_SRC_SPLL = 4,
-	EXYNOS_SRC_IPLL = 5,
-	EXYNOS_SRC_EPLL = 6,
-	EXYNOS_SRC_RPLL = 7,
-};
+#define IPLL	10
 
 /* *
  * This structure is to store the src bit, div bit and prediv bit