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authorJulius Werner <jwerner@chromium.org>2013-08-15 17:34:45 -0700
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-08-12 22:05:17 +0200
commit79bff70ac829f45b27650671f9c33028c4b8f6c7 (patch)
tree39181ed154fa3f8733b4623b1e210fe3db355f2c /src/cpu/samsung/exynos5420/cpu.c
parente9738dbe2bb564f7be7930aa5b01e9ae3c1e2288 (diff)
downloadcoreboot-79bff70ac829f45b27650671f9c33028c4b8f6c7.tar.xz
exynos5: Refactor board-specific parts out of USB PHY code
This patch moves around some of the existing Exynos5 USB 2.0 PHY code to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS GPIOs (which are completely board-specific) into the mainboard code and makes sure to only initialize PHYs on the boards that actually need them. It also removes the USB 3.0 PLL hack that was needed on Snow from the Pit and Kirby boards (which do not have that PLL anymore). Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66887 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/samsung/exynos5420/cpu.c')
-rw-r--r--src/cpu/samsung/exynos5420/cpu.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index 3b87c6e0ee..f3d5282b6b 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -30,7 +30,6 @@
#include "fimd.h"
#include "cpu.h"
#include "clk.h"
-#include "usb.h"
#include "chip.h"
#include <ec/google/chromeec/ec.h>
@@ -181,8 +180,6 @@ static void cpu_init(device_t dev)
{
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
cpu_id, get_arm_clk() / 1000000);
-
- usb_init(dev);
}
static void cpu_noop(device_t dev)