exynos5: Refactor crazy old U-Boot base address macros away

All this samsung_get_base_address_of_device_with_a_really_long_name()
boilerplate makes my eyes bleed... I think there are so much cleaner
ways to do this. Unfortunately changing this ends up touching nearly
every Exynos5 file, but I hope you agree that it's worth it (and the
sooner we get it over with, the better... I can't bring myself to make
another device fit into that ugly scheme).

This also removes the redundant EXYNOS5 base address definitions from
the 5420 directory when there are EXYNOS5420 ones, to avoid complete
confusion. The new scheme tries to use EXYNOS5 for base addresses and
exynos5 for types that are common between the two processors, and
EXYNOS5420/exynos5420 for things that have changes (although I probably
didn't catch all differences).

Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167579
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6632
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 18 insertions, 0 deletions

diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h
index 1a6adca6f9..fa7482ae89 100644
--- a/src/cpu/samsung/exynos5420/dmc.h
+++ b/src/cpu/samsung/exynos5420/dmc.h
@@ -20,6 +20,8 @@
 
 #define DMC_INTERLEAVE_SIZE		0x1f
 
+#define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
+
 /* CONCONTROL register fields */
 #define CONCONTROL_DFI_INIT_START_SHIFT	28
 #define CONCONTROL_RD_FETCH_SHIFT	12
@@ -69,6 +71,9 @@
 #define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
 
 #ifndef __ASSEMBLER__
+
+#include "cpu.h"
+
 struct exynos5_dmc {
 	uint32_t concontrol;
 	uint32_t memcontrol;
@@ -202,6 +207,9 @@ struct exynos5_dmc {
 	uint32_t pmcnt3_ppc;	/* 0xe140 */
 } __attribute__((packed));
 
+static struct exynos5_dmc * const exynos_drex0 = (void *)EXYNOS5420_DMC_DREXI_0;
+static struct exynos5_dmc * const exynos_drex1 = (void *)EXYNOS5420_DMC_DREXI_1;
+
 struct exynos5_phy_control {
 	uint32_t phy_con0;
 	uint32_t phy_con1;
@@ -249,6 +257,11 @@ struct exynos5_phy_control {
 	uint32_t phy_con42;
 } __attribute__((packed));
 
+static struct exynos5_phy_control * const exynos_phy0_control =
+		(void *)EXYNOS5_DMC_PHY0_BASE;
+static struct exynos5_phy_control * const exynos_phy1_control =
+		(void *)EXYNOS5_DMC_PHY1_BASE;
+
 struct exynos5_tzasc {
 	uint8_t res1[0xf00];
 	uint32_t membaseconfig0;
@@ -258,6 +271,11 @@ struct exynos5_tzasc {
 	uint32_t memconfig1;
 } __attribute__((packed));
 
+static struct exynos5_tzasc * const exynos_tzasc0 =
+		(void *)EXYNOS5420_DMC_TZASC_0;
+static struct exynos5_tzasc * const exynos_tzasc1 =
+		(void *)EXYNOS5420_DMC_TZASC_1;
+
 enum ddr_mode {
 	/* This is in order of ctrl_ddr_mode values. Do not change. */
 	DDR_MODE_DDR2	= 0x0,