Pit: graphics

This includes the new dp code, which is better, and the fimd code,
which is changed and improved. We took the chance to remove un-needed
files, and also to remove some foolish u-boot habits, but not all of
them. That will take time.

With these changes we get graphics.

Since the only mainboards we have with 16 bit graphics are 5:6:5,
adjust edid.c to just use that format. If at some future time we need
4:4:4, which seems unlikely, we'll need to add a function to adjust
the lb_framebuffer. Note that you can't just divine this from the EDID,
as the graphics pipe format need not match the actual final format used.

The EDID reading works. We've been requested to support hard-coded
EDIDs and that will come in the next revision. Currently the hard-coded
EDID is ignored for testing.

Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64240
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 118 insertions, 43 deletions

diff --git a/src/cpu/samsung/exynos5420/fimd.h b/src/cpu/samsung/exynos5420/fimd.h
index 661ed9ec6f..7d6897958b 100644
--- a/src/cpu/samsung/exynos5420/fimd.h
+++ b/src/cpu/samsung/exynos5420/fimd.h
@@ -25,39 +25,39 @@
 /* FIMD register map */
 struct exynos5_fimd {
 	/* This is an incomplete list. Add registers as and when required */
-	unsigned int vidcon0;
-	unsigned char res1[0x1c];
-	unsigned int wincon0;
-	unsigned int wincon1;
-	unsigned int wincon2;
-	unsigned int wincon3;
-	unsigned int wincon4;
-	unsigned int shadowcon;
-	unsigned char res2[0x8];
-	unsigned int vidosd0a;
-	unsigned int vidosd0b;
-	unsigned int vidosd0c;
-	unsigned char res3[0x54];
-	unsigned int vidw00add0b0;
-	unsigned char res4[0x2c];
-	unsigned int vidw00add1b0;
-	unsigned char res5[0x2c];
-	unsigned int vidw00add2;
-	unsigned char res6[0x3c];
-	unsigned int w1keycon0;
-	unsigned int w1keycon1;
-	unsigned int w2keycon0;
-	unsigned int w2keycon1;
-	unsigned int w3keycon0;
-	unsigned int w3keycon1;
-	unsigned int w4keycon0;
-	unsigned int w4keycon1;
-	unsigned char res7[0x20];
-	unsigned int win0map;
-	unsigned char res8[0xdc];
-	unsigned int blendcon;
-	unsigned char res9[0x18];
-	unsigned int dpclkcon;
+	u32 vidcon0;
+	u8 res1[0x1c];
+	u32 wincon0;
+	u32 wincon1;
+	u32 wincon2;
+	u32 wincon3;
+	u32 wincon4;
+	u32 shadowcon;
+	u8 res2[0x8];
+	u32 vidosd0a;
+	u32 vidosd0b;
+	u32 vidosd0c;
+	u8 res3[0x54];
+	u32 vidw00add0b0;
+	u8 res4[0x2c];
+	u32 vidw00add1b0;
+	u8 res5[0x2c];
+	u32 vidw00add2;
+	u8 res6[0x3c];
+	u32 w1keycon0;
+	u32 w1keycon1;
+	u32 w2keycon0;
+	u32 w2keycon1;
+	u32 w3keycon0;
+	u32 w3keycon1;
+	u32 w4keycon0;
+	u32 w4keycon1;
+	u8 res7[0x20];
+	u32 win0map;
+	u8 res8[0xdc];
+	u32 blendcon;
+	u8 res9[0x18];
+	u32 dpclkcon;
 };
 
 #define W0_SHADOW_PROTECT	(0x1 << 10)
@@ -86,7 +86,7 @@ struct exynos5_fimd_panel {
 	unsigned int upper_margin;	/* Vertical Backporch */
 	unsigned int lower_margin;	/* Vertical frontporch */
 	unsigned int vsync;		/* Vertical Sync Pulse Width */
-	unsigned int left_margin;	/* Horizantal Backporch */
+	unsigned int left_margin;	/* Horizontal Backporch */
 	unsigned int right_margin;	/* Horizontal Frontporch */
 	unsigned int hsync;		/* Horizontal Sync Pulse Width */
 	unsigned int xres;		/* X Resolution */
@@ -95,15 +95,15 @@ struct exynos5_fimd_panel {
 
 /* LCDIF Register Map */
 struct exynos5_disp_ctrl {
-	unsigned int vidout_con;
-	unsigned int vidcon1;
-	unsigned char res1[0x8];
-	unsigned int vidtcon0;
-	unsigned int vidtcon1;
-	unsigned int vidtcon2;
-	unsigned int vidtcon3;
-	unsigned char res2[0x184];
-	unsigned int trigcon;
+	u32 vidout_con;
+	u32 vidcon1;
+	u8 res1[0x8];
+	u32 vidtcon0;
+	u32 vidtcon1;
+	u32 vidtcon2;
+	u32 vidtcon3;
+	u8 res2[0x184];
+	u32 trigcon;
 };
 
 #define VCLK_RISING_EDGE		(1 << 7)
@@ -135,4 +135,79 @@ struct exynos5_disp_ctrl {
 
 #define OSD_RIGHTBOTX_F_OFFSET		11
 #define OSD_RIGHTBOTY_F_OFFSET		0
+
+#define FIMD_CTRL ((struct exynos_fb *)0x14400000)
+
+/* from u-boot fb.h. It needs to be merged with these dp structs maybe. */
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
+typedef struct vidinfo {
+	u16 vl_col;		/* Number of columns (i.e. 640) */
+	u16 vl_row;		/* Number of rows (i.e. 480) */
+	u16 vl_width;	/* Width of display area in millimeters */
+	u16 vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u8 vl_freq;		/* Frequency */
+	u8 vl_clkp;		/* Clock polarity */
+	u8 vl_oep;		/* Output Enable polarity */
+	u8 vl_hsp;		/* Horizontal Sync polarity */
+	u8 vl_vsp;		/* Vertical Sync polarity */
+	u8 vl_dp;		/* Data polarity */
+	u8 vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u8 vl_hspw;		/* Horz sync pulse width */
+	u8 vl_hfpd;		/* Wait before of line */
+	u8 vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u8	vl_vspw;	/* Vertical sync pulse width */
+	u8	vl_vfpd;	/* Wait before of frame */
+	u8	vl_vbpd;	/* Wait end of frame */
+	u8  vl_cmd_allow_len; /* Wait end of frame */
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int dp_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+	unsigned int rgb_mode;
+	unsigned int resolution;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+	void *screen_base;
+	void	*cmap;		/* Points at 8 to 16 bit conversion map. */
+} vidinfo_t;
+
+/* fimd.c */
+void exynos_set_trigger(void);
+int exynos_is_i80_frame_done(void);
+void exynos_fimd_lcd_off(void);
+void exynos_fimd_window_off(unsigned int win_id);
+unsigned long exynos_fimd_calc_fbsize(vidinfo_t *vid);
+void exynos_fimd_lcd_disable(void);
+void exynos_fimd_lcd_init(vidinfo_t *vid);
+
 #endif