exynos5: Refactor crazy old U-Boot base address macros away

All this samsung_get_base_address_of_device_with_a_really_long_name()
boilerplate makes my eyes bleed... I think there are so much cleaner
ways to do this. Unfortunately changing this ends up touching nearly
every Exynos5 file, but I hope you agree that it's worth it (and the
sooner we get it over with, the better... I can't bring myself to make
another device fit into that ugly scheme).

This also removes the redundant EXYNOS5 base address definitions from
the 5420 directory when there are EXYNOS5420 ones, to avoid complete
confusion. The new scheme tries to use EXYNOS5 for base addresses and
exynos5 for types that are common between the two processors, and
EXYNOS5420/exynos5420 for things that have changes (although I probably
didn't catch all differences).

Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167579
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6632
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 52 insertions, 66 deletions

diff --git a/src/cpu/samsung/exynos5420/gpio.h b/src/cpu/samsung/exynos5420/gpio.h
index 0011904eb5..4cf8e57249 100644
--- a/src/cpu/samsung/exynos5420/gpio.h
+++ b/src/cpu/samsung/exynos5420/gpio.h
@@ -20,6 +20,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_GPIO_H
 #define CPU_SAMSUNG_EXYNOS5420_GPIO_H
 
+#include "cpu.h"
+
 struct gpio_bank {
 	unsigned int	con;
 	unsigned int	dat;
@@ -52,73 +54,57 @@ struct gpio_bank {
 #define GPIO_DRV_FAST	0x0
 #define GPIO_DRV_SLOW	0x1
 
-#define EXYNOS5_GPIO_BASE0	0x13400000
-#define EXYNOS5_GPIO_BASE1	0x13400c00
-#define EXYNOS5_GPIO_BASE2	0x13410000
-#define EXYNOS5_GPIO_BASE3	0x14000000
-#define EXYNOS5_GPIO_BASE4	0x14010000
-#define EXYNOS5_GPIO_BASE5	0x03860000
-
 enum exynos5_gpio_port {
-	/*
-	 * Ordered by base address + offset.
-	 * ETC registers are special, thus not included.
-	 */
-
-	/* base == EXYNOS_GPIO_BASE0 */
-	EXYNOS5_GPY7 = EXYNOS5_GPIO_BASE0 + 0x0000,
-
-	/* base == EXYNOS_GPIO_BASE1 */
-	EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE1 + 0x0000,
-	EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE1 + 0x0020,
-	EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE1 + 0x0040,
-	EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE1 + 0x0060,
-
-	/* base == EXYNOS_GPIO_BASE2 */
-	EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE2 + 0x0000,
-	EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE2 + 0x0020,
-	EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE2 + 0x0040,
-	EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE2 + 0x0060,
-	EXYNOS5_GPC4 = EXYNOS5_GPIO_BASE2 + 0x0080,
-
-	EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE2 + 0x00a0,
-
-	EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE2 + 0x00c0,
-	EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE2 + 0x00e0,
-	EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE2 + 0x0100,
-	EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE2 + 0x0120,
-	EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE2 + 0x0140,
-	EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE2 + 0x0160,
-	EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE2 + 0x0180,
-
-	/* base == EXYNOS5_GPIO_BASE3 */
-	EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE3 + 0x0000,
-	EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE3 + 0x0020,
-
-	EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE3 + 0x0040,
-	EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE3 + 0x0060,
-
-	EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE3 + 0x0080,
-	EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE3 + 0x00a0,
-	EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE3 + 0x00c0,
-
-	EXYNOS5_GPJ4 = EXYNOS5_GPIO_BASE3 + 0x00e0,
-
-	/* base == EXYNOS5_GPIO_BASE4 */
-	EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE4 + 0x0000,
-	EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE4 + 0x0020,
-	EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE4 + 0x0040,
-
-	EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE4 + 0x0060,
-	EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE4 + 0x0080,
-	EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE4 + 0x00a0,
-	EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE4 + 0x00c0,
-	EXYNOS5_GPB4 = EXYNOS5_GPIO_BASE4 + 0x00e0,
-
-	EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE4 + 0x0100,
-
-	/* base == EXYNOS5_GPIO_BASE5 */
-	EXYNOS5_GPZ0 = EXYNOS5_GPIO_BASE5 + 0x0000,
+	EXYNOS5_GPY7 = EXYNOS5420_GPIO_PART1_BASE + 0x0000,
+
+	EXYNOS5_GPX0 = EXYNOS5420_GPIO_PART2_BASE + 0x0000,
+	EXYNOS5_GPX1 = EXYNOS5420_GPIO_PART2_BASE + 0x0020,
+	EXYNOS5_GPX2 = EXYNOS5420_GPIO_PART2_BASE + 0x0040,
+	EXYNOS5_GPX3 = EXYNOS5420_GPIO_PART2_BASE + 0x0060,
+
+	EXYNOS5_GPC0 = EXYNOS5420_GPIO_PART3_BASE + 0x0000,
+	EXYNOS5_GPC1 = EXYNOS5420_GPIO_PART3_BASE + 0x0020,
+	EXYNOS5_GPC2 = EXYNOS5420_GPIO_PART3_BASE + 0x0040,
+	EXYNOS5_GPC3 = EXYNOS5420_GPIO_PART3_BASE + 0x0060,
+	EXYNOS5_GPC4 = EXYNOS5420_GPIO_PART3_BASE + 0x0080,
+
+	EXYNOS5_GPD1 = EXYNOS5420_GPIO_PART3_BASE + 0x00a0,
+
+	EXYNOS5_GPY0 = EXYNOS5420_GPIO_PART3_BASE + 0x00c0,
+	EXYNOS5_GPY1 = EXYNOS5420_GPIO_PART3_BASE + 0x00e0,
+	EXYNOS5_GPY2 = EXYNOS5420_GPIO_PART3_BASE + 0x0100,
+	EXYNOS5_GPY3 = EXYNOS5420_GPIO_PART3_BASE + 0x0120,
+	EXYNOS5_GPY4 = EXYNOS5420_GPIO_PART3_BASE + 0x0140,
+	EXYNOS5_GPY5 = EXYNOS5420_GPIO_PART3_BASE + 0x0160,
+	EXYNOS5_GPY6 = EXYNOS5420_GPIO_PART3_BASE + 0x0180,
+
+	EXYNOS5_GPE0 = EXYNOS5420_GPIO_PART4_BASE + 0x0000,
+	EXYNOS5_GPE1 = EXYNOS5420_GPIO_PART4_BASE + 0x0020,
+
+	EXYNOS5_GPF0 = EXYNOS5420_GPIO_PART4_BASE + 0x0040,
+	EXYNOS5_GPF1 = EXYNOS5420_GPIO_PART4_BASE + 0x0060,
+
+	EXYNOS5_GPG0 = EXYNOS5420_GPIO_PART4_BASE + 0x0080,
+	EXYNOS5_GPG1 = EXYNOS5420_GPIO_PART4_BASE + 0x00a0,
+	EXYNOS5_GPG2 = EXYNOS5420_GPIO_PART4_BASE + 0x00c0,
+
+	EXYNOS5_GPJ4 = EXYNOS5420_GPIO_PART4_BASE + 0x00e0,
+
+	/* base == EXYNOS5420_GPIO_PART5_BASE */
+	EXYNOS5_GPA0 = EXYNOS5420_GPIO_PART5_BASE + 0x0000,
+	EXYNOS5_GPA1 = EXYNOS5420_GPIO_PART5_BASE + 0x0020,
+	EXYNOS5_GPA2 = EXYNOS5420_GPIO_PART5_BASE + 0x0040,
+
+	EXYNOS5_GPB0 = EXYNOS5420_GPIO_PART5_BASE + 0x0060,
+	EXYNOS5_GPB1 = EXYNOS5420_GPIO_PART5_BASE + 0x0080,
+	EXYNOS5_GPB2 = EXYNOS5420_GPIO_PART5_BASE + 0x00a0,
+	EXYNOS5_GPB3 = EXYNOS5420_GPIO_PART5_BASE + 0x00c0,
+	EXYNOS5_GPB4 = EXYNOS5420_GPIO_PART5_BASE + 0x00e0,
+
+	EXYNOS5_GPH0 = EXYNOS5420_GPIO_PART5_BASE + 0x0100,
+
+	/* base == EXYNOS5420_GPIO_PART6_BASE */
+	EXYNOS5_GPZ0 = EXYNOS5420_GPIO_PART6_BASE + 0x0000,
 };
 
 enum {