trustzone: Pull trustzone init out of cpu.c and do it in romstage.

Trustzone needs to be initialized/disabled both on boot and on wake, so it
needs to be done before ramstage which doesn't run on wake. cpu.c isn't
compiled into romstage and fixing that causes other problems, so the trustzone
functions were split out.

Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/169817
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6666
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

5 files changed, 124 insertions, 76 deletions

diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc
index bb6d8fed3a..897944cf46 100644
--- a/src/cpu/samsung/exynos5420/Makefile.inc
+++ b/src/cpu/samsung/exynos5420/Makefile.inc
@@ -35,6 +35,7 @@ romstage-y += timer.c
 romstage-y += i2c.c
 #romstage-y += wdt.c
 romstage-y += cbmem.c
+romstage-y += trustzone.c
 
 ramstage-y += spi.c alternate_cbfs.c
 ramstage-y += clock.c
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index a0c33ca378..bfb8421910 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -37,26 +37,6 @@
 static unsigned int cpu_id;
 static unsigned int cpu_rev;
 
-/* Setting TZPC[TrustZone Protection Controller]
- * We pretty much disable it all, as the kernel
- * expects it that way -- and that's not the default.
- */
-static void tzpc_init(void)
-{
-	struct exynos_tzpc *tzpc;
-	unsigned int addr;
-
-	for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
-		tzpc = (struct exynos_tzpc *)addr;
-		if (addr == TZPC0_BASE)
-			writel(R0SIZE, &tzpc->r0size);
-		writel(DECPROTXSET, &tzpc->decprot0set);
-		writel(DECPROTXSET, &tzpc->decprot1set);
-		writel(DECPROTXSET, &tzpc->decprot2set);
-		writel(DECPROTXSET, &tzpc->decprot3set);
-	}
-}
-
 static void set_cpu_id(void)
 {
 	u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12;
@@ -172,8 +152,6 @@ static void cpu_enable(device_t dev)
 	exynos_displayport_init(dev, lcdbase, fb_size);
 
 	set_cpu_id();
-
-	tzpc_init();
 }
 
 static void cpu_init(device_t dev)
diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h
index 847800db5e..5b5c731bf0 100644
--- a/src/cpu/samsung/exynos5420/cpu.h
+++ b/src/cpu/samsung/exynos5420/cpu.h
@@ -75,34 +75,6 @@
 /* Marker values stored at the bottom of IRAM stack by SPL */
 #define EXYNOS5_SPL_MARKER	0xb004f1a9	/* hexspeak word: bootflag */
 
-/* Distance between each Trust Zone PC register set */
-#define TZPC_BASE_OFFSET		0x10000
-/* TZPC : Register Offsets */
-#define TZPC0_BASE		0x10100000
-#define TZPC1_BASE		0x10110000
-#define TZPC2_BASE		0x10120000
-#define TZPC3_BASE		0x10130000
-#define TZPC4_BASE		0x10140000
-#define TZPC5_BASE		0x10150000
-#define TZPC6_BASE		0x10160000
-#define TZPC7_BASE		0x10170000
-#define TZPC8_BASE		0x10180000
-#define TZPC9_BASE		0x10190000
-#define TZPC10_BASE		0x100E0000
-#define TZPC11_BASE		0x100F0000
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE			0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET		0xFF
-
 #define RST_FLAG_VAL			0xfcba0d10
 
 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
@@ -115,32 +87,6 @@ extern struct tmu_info exynos5420_tmu_info;
 #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
 #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
 
-struct exynos_tzpc {
-	u32 r0size;
-	u8 res1[0x7FC];
-	u32 decprot0stat;
-	u32 decprot0set;
-	u32 decprot0clr;
-	u32 decprot1stat;
-	u32 decprot1set;
-	u32 decprot1clr;
-	u32 decprot2stat;
-	u32 decprot2set;
-	u32 decprot2clr;
-	u32 decprot3stat;
-	u32 decprot3set;
-	u32 decprot3clr;
-	u8 res2[0x7B0];
-	u32 periphid0;
-	u32 periphid1;
-	u32 periphid2;
-	u32 periphid3;
-	u32 pcellid0;
-	u32 pcellid1;
-	u32 pcellid2;
-	u32 pcellid3;
-};
-
 static inline u32 get_fb_base_kb(void)
 {
 	return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
diff --git a/src/cpu/samsung/exynos5420/trustzone.c b/src/cpu/samsung/exynos5420/trustzone.c
new file mode 100644
index 0000000000..7b1489a1a6
--- /dev/null
+++ b/src/cpu/samsung/exynos5420/trustzone.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "trustzone.h"
+
+/* Setting TZPC[TrustZone Protection Controller]
+ * We pretty much disable it all, as the kernel
+ * expects it that way -- and that's not the default.
+ */
+void trustzone_init(void)
+{
+	struct exynos_tzpc *tzpc;
+	unsigned int addr;
+
+	for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+		tzpc = (struct exynos_tzpc *)addr;
+		if (addr == TZPC0_BASE)
+			writel(R0SIZE, &tzpc->r0size);
+		writel(DECPROTXSET, &tzpc->decprot0set);
+		writel(DECPROTXSET, &tzpc->decprot1set);
+		writel(DECPROTXSET, &tzpc->decprot2set);
+		writel(DECPROTXSET, &tzpc->decprot3set);
+	}
+}
diff --git a/src/cpu/samsung/exynos5420/trustzone.h b/src/cpu/samsung/exynos5420/trustzone.h
new file mode 100644
index 0000000000..69e683aeba
--- /dev/null
+++ b/src/cpu/samsung/exynos5420/trustzone.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H
+#define CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H
+
+#include <stdint.h>
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET		0x10000
+/* TZPC : Register Offsets */
+#define TZPC0_BASE		0x10100000
+#define TZPC1_BASE		0x10110000
+#define TZPC2_BASE		0x10120000
+#define TZPC3_BASE		0x10130000
+#define TZPC4_BASE		0x10140000
+#define TZPC5_BASE		0x10150000
+#define TZPC6_BASE		0x10160000
+#define TZPC7_BASE		0x10170000
+#define TZPC8_BASE		0x10180000
+#define TZPC9_BASE		0x10190000
+#define TZPC10_BASE		0x100E0000
+#define TZPC11_BASE		0x100F0000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+
+struct exynos_tzpc {
+	u32 r0size;
+	u8 res1[0x7FC];
+	u32 decprot0stat;
+	u32 decprot0set;
+	u32 decprot0clr;
+	u32 decprot1stat;
+	u32 decprot1set;
+	u32 decprot1clr;
+	u32 decprot2stat;
+	u32 decprot2set;
+	u32 decprot2clr;
+	u32 decprot3stat;
+	u32 decprot3set;
+	u32 decprot3clr;
+	u8 res2[0x7B0];
+	u32 periphid0;
+	u32 periphid1;
+	u32 periphid2;
+	u32 periphid3;
+	u32 pcellid0;
+	u32 pcellid1;
+	u32 pcellid2;
+	u32 pcellid3;
+};
+
+void trustzone_init(void);
+
+#endif	/* CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H */