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| author | Julius Werner <jwerner@chromium.org> | 2013-09-19 20:15:45 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-18 19:04:08 +0200 |
| commit | f0cd03c142013e0f50705a1c8741c0f02bea43de (patch) | |
| tree | bad38cceb315402dc71246f3ecbc4955bb36c1dd /src/cpu/samsung | |
| parent | 12b121f3fef61d6a346c2575266a9cb46bb9d31f (diff) | |
| download | coreboot-f0cd03c142013e0f50705a1c8741c0f02bea43de.tar.xz | |
exynos5420: Don't map low addresses that lead nowhere
I just spent half a day (including the time to implement a stack dumper)
to figure out that I am reading from a NULL pointer. A problem this
simple should be more easy to catch. Let's mark the address range below
SRAM as uncached so that the MMU can yell at you right away for being
the bad programmer you are when you access a NULL pointer.
Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170112
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6650
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/samsung')
| -rw-r--r-- | src/cpu/samsung/exynos5420/bootblock.c | 4 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/cpu.h | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index 2c42b03ce7..97e85f1fd6 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -24,7 +24,7 @@ #include "cpu.h" /* convenient shorthand (in MB) */ -#define SRAM_START (0x02020000 >> 20) +#define SRAM_START (EXYNOS5_SRAM_BASE >> 20) #define SRAM_SIZE 1 #define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */ @@ -43,7 +43,7 @@ void bootblock_cpu_init(void) /* set up dcache and MMU */ mmu_init(); - mmu_config_range(0, SRAM_START, DCACHE_OFF); + mmu_disable_range(0, SRAM_START); mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); dcache_mmu_enable(); diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index e3c7f1be38..847800db5e 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -22,6 +22,8 @@ #include <arch/io.h> +#define EXYNOS5_SRAM_BASE 0x02020000 + /* Base address registers */ #define EXYNOS5420_GPIO_PART6_BASE 0x03860000 /* Z0 */ #define EXYNOS5_PRO_ID 0x10000000 |