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| author | Hung-Te Lin <hungte@chromium.org> | 2013-08-06 10:48:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 22:45:11 +0100 |
| commit | c0491d4fb55eaa7a18cb46dfab886eeb195b9323 (patch) | |
| tree | 5f88d30d51bba5ec680c054612fe7ac2f3f89ac3 /src/cpu/samsung | |
| parent | c0d5eb2a332a7db1311517032e6f9ce1d5b91551 (diff) | |
| download | coreboot-c0491d4fb55eaa7a18cb46dfab886eeb195b9323.tar.xz | |
armv7/exynos: Fix and remove memory reset workarounds
The memory corruption problem in Exynos suspend/resume process is caused by two
things together: PHY_RESET and MRS command.
After stop sending MRS on resume, we can now remove the workaround of skipping
PHY_RESET.
Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c
Reviewed-on: https://gerrit.chromium.org/gerrit/64736
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4433
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/samsung')
| -rw-r--r-- | src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 10 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 12 |
2 files changed, 17 insertions, 5 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index e3d46ab2d5..f2c228d339 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -158,8 +158,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Send PALL command */ dmc_config_prech(mem, dmc); - /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, dmc); + if (mem_reset) { + /* Send NOP, MRS and ZQINIT commands. + * Sending MRS command will reset the DRAM. We should not be + * reseting the DRAM after resume, this will lead to memory + * corruption as DRAM content is lost after DRAM reset + */ + dmc_config_mrs(mem, dmc); + } if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index 74ee7e93a1..ebfe1e1a0f 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -184,9 +184,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->timing_power, &drex0->timingpower); writel(mem->timing_power, &drex1->timingpower); - /* Send NOP, MRS and ZQINIT commands */ - dmc_config_mrs(mem, drex0); - dmc_config_mrs(mem, drex1); + /* Send NOP, MRS and ZQINIT commands. + * Sending MRS command will reset the DRAM. We should not be + * reseting the DRAM after resume, this will lead to memory + * corruption as DRAM content is lost after DRAM reset. + */ + if (reset) { + dmc_config_mrs(mem, drex0); + dmc_config_mrs(mem, drex1); + } if (mem->gate_leveling_enable) { |