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authorpchandri <preetham.chandrian@intel.com>2016-01-11 15:22:45 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-22 12:59:59 +0100
commitf9495eae2c9a0894fb7a8917779880830b27a224 (patch)
treeb15fcce34cbafe31013fdf2306ca4c059a383d14 /src/cpu/ti/am335x/dmtimer.c
parent2cd9c05dc10462c105d889cecc148b5d87ac53fb (diff)
downloadcoreboot-f9495eae2c9a0894fb7a8917779880830b27a224.tar.xz
intel/skylake: Thermal Design Power PL1 and PL2 Config Changes
Override the default PL2 values with one recommended by Intel. Disable PL1 configuration via MMIO register. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. Change-Id: I10742f91cc7179de1482d42392338976e8082afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731 Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321392 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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