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| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-04 10:19:05 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 19:34:57 +0000 |
| commit | cce557b7934c2560ac2ae33e06b6039acd4e6fb9 (patch) | |
| tree | 1ea741a6e1baf9f31ac9424fb0398e27fdc1237e /src/cpu/ti | |
| parent | 4de29d48edb2c760332def9004989d6cdf002f02 (diff) | |
| download | coreboot-cce557b7934c2560ac2ae33e06b6039acd4e6fb9.tar.xz | |
x86: link ramstage like the other architectures
All the other architectures are using the memlayout
for linking ramstage. The last piece to align x86 is
to use arch/header.ld and the macros within memlayout.h
to automaticaly generate the necessary linker script.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11508
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/ti')
0 files changed, 0 insertions, 0 deletions