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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/cpu/via/car
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
downloadcoreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/via/car')
-rw-r--r--src/cpu/via/car/cache_as_ram.inc18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 8a12c8fa48..8bc274b381 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -179,12 +179,12 @@ testok: movb $0x40,%al
pushl %eax /* bist */
call main
- /*
+ /*
* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
* get STACK up, we restore that. It is only needed if we
* want to go back.
*/
-
+
/* We don't need cache as ram for now on */
/* disable cache */
movl %cr0, %eax
@@ -207,7 +207,7 @@ testok: movb $0x40,%al
movl $(0 | 6), %eax
//movl $(0 | MTRR_TYPE_WRBACK), %eax
wrmsr
-
+
/* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
* If 1M cacheable, then when S3 resume, there is stange color on
* screen for 2 sec. suppose problem of a0000-dfffff and cache.
@@ -218,7 +218,7 @@ testok: movb $0x40,%al
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
wrmsr
-
+
movl $0x202, %ecx
xorl %edx, %edx
movl $(0x80000 | 6), %eax
@@ -229,7 +229,7 @@ testok: movb $0x40,%al
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
wrmsr
-
+
movl $0x204, %ecx
xorl %edx, %edx
movl $(0xc0000 | 6), %eax
@@ -239,8 +239,8 @@ testok: movb $0x40,%al
movl $0x205, %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
- wrmsr
-
+ wrmsr
+
/* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
movl $0x206, %ecx
xorl %edx, %edx
@@ -267,7 +267,7 @@ testok: movb $0x40,%al
__main:
post_code(0x11)
cld /* clear direction flag */
-
+
movl %ebp, %esi
movl $ROMSTAGE_STACK, %esp
@@ -275,7 +275,7 @@ __main:
pushl %esi
call copy_and_run
-.Lhlt:
+.Lhlt:
post_code(0xee)
hlt
jmp .Lhlt