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authorStefan Reinauer <stepan@coresystems.de>2011-01-19 06:54:42 +0000
committerStefan Reinauer <stepan@openbios.org>2011-01-19 06:54:42 +0000
commit7b0500c24ca103e8f8d802b476517afc2ac8eef5 (patch)
tree9288cd7a3ea130d50e151455ea9c72bf07fd29a2 /src/cpu/via/car
parent5bb9fd6e4dae32f86a07676228034d3828820037 (diff)
downloadcoreboot-7b0500c24ca103e8f8d802b476517afc2ac8eef5.tar.xz
Revert r5902 to make code more readable again. At least three people like to
have this go away again. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Kevin O'Connor <kevin@koconnor.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/via/car')
-rw-r--r--src/cpu/via/car/cache_as_ram.inc27
1 files changed, 20 insertions, 7 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index c3c1cb7664..fcd6c45e5f 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -25,18 +25,21 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <cpu/x86/car.h>
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
- save_bist_result()
+ /* Save the BIST result. */
+ movl %eax, %ebp
CacheAsRam:
- disable_cache()
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
invd
/* Set the default memory type and enable fixed and variable MTRRs. */
@@ -139,7 +142,10 @@ clear_fixed_var_mtrr_out:
movl $(MTRRdefTypeEn), %eax
wrmsr
- enable_cache()
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
+ movl %eax, %cr0
/* Read the range with lodsl. */
cld
@@ -195,7 +201,8 @@ testok:
jne stackerr
#endif
- restore_bist_result()
+ /* Restore the BIST result. */
+ movl %ebp, %eax
/* We need to set EBP? No need. */
movl %esp, %ebp
@@ -210,7 +217,10 @@ testok:
/* We don't need CAR from now on. */
- disable_cache()
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
/* Set the default memory type and enable variable MTRRs. */
/* TODO: Or also enable fixed MTRRs? Bug in the code? */
@@ -242,7 +252,10 @@ testok:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
- enable_cache()
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
+ movl %eax, %cr0
invd
/* Clear boot_complete flag. */