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author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-21 10:12:15 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-08-23 15:43:58 +0200 |
commit | d6e96864c9245b82222dada6fea2b89ccb7fecfd (patch) | |
tree | 9d850d9cfc15d19792da114d426009cc6fb208fa /src/cpu/via/nano | |
parent | 38424987c6d19015e4572d5371a0f9f621fc46fa (diff) | |
download | coreboot-d6e96864c9245b82222dada6fea2b89ccb7fecfd.tar.xz |
src/cpu: Capitalize CPU, APIC and IOAPIC typo fix
Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16276
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Diffstat (limited to 'src/cpu/via/nano')
-rw-r--r-- | src/cpu/via/nano/nano_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index cdf05890e9..e84ef28b19 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -180,7 +180,7 @@ static void nano_init(struct device *dev) /* Set up Memory Type Range Registers */ x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local CPU apics */ + /* Enable the local CPU APICs */ setup_lapic(); } |