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authorMyles Watson <mylesgw@gmail.com>2009-10-23 18:22:27 +0000
committerMyles Watson <mylesgw@gmail.com>2009-10-23 18:22:27 +0000
commit707fad0508ffabc6a5137e35d0248ccaa188dea9 (patch)
treebbbb85ec02fda217f605b8c31aa03af71e655d77 /src/cpu/via
parent35ed0e7ea3d9bd6641c719cf4489bfa408e48972 (diff)
downloadcoreboot-707fad0508ffabc6a5137e35d0248ccaa188dea9.tar.xz
White space and comment fixes for cache_as_ram.inc files so it's easier to spot
differences. Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/via')
-rw-r--r--src/cpu/via/car/cache_as_ram.inc145
1 files changed, 73 insertions, 72 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 3e5729aa1f..f59596d171 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -1,6 +1,6 @@
-/*
+/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Eswar Nallusamy, LANL
* Copyright (C) 2005 Tyan
@@ -10,153 +10,154 @@
* Copyright (C) 2007,2008 Carl-Daniel Hailfinger
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
- *
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
- *
+ *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase CONFIG_DCACHE_RAM_BASE
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
+#define CacheBase CONFIG_DCACHE_RAM_BASE
-#include <cpu/x86/mtrr.h>
+#include <cpu/x86/mtrr.h>
/* Save the BIST result */
- movl %eax, %ebp
+ movl %eax, %ebp
CacheAsRam:
/* disable cache */
- movl %cr0, %eax
- orl $(0x1<<30),%eax
- movl %eax,%cr0
+ movl %cr0, %eax
+ orl $(0x1<<30),%eax
+ movl %eax,%cr0
invd
/* Set the default memory type and enable fixed and variable MTRRs */
- movl $MTRRdefType_MSR, %ecx
- xorl %edx, %edx
+ movl $MTRRdefType_MSR, %ecx
+ xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */
- movl $0x00000c00, %eax
+ movl $0x00000c00, %eax
wrmsr
/* Clear all MTRRs */
- xorl %edx, %edx
- movl $fixed_mtrr_msr, %esi
+ xorl %edx, %edx
+ movl $fixed_mtrr_msr, %esi
+
clear_fixed_var_mtrr:
- lodsl (%esi), %eax
- testl %eax, %eax
- jz clear_fixed_var_mtrr_out
+ lodsl (%esi), %eax
+ testl %eax, %eax
+ jz clear_fixed_var_mtrr_out
- movl %eax, %ecx
- xorl %eax, %eax
+ movl %eax, %ecx
+ xorl %eax, %eax
wrmsr
- jmp clear_fixed_var_mtrr
+ jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* MTRRPhysBase */
- movl $0x200, %ecx
- xorl %edx, %edx
- movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
+ movl $0x200, %ecx
+ xorl %edx, %edx
+ movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
wrmsr
/* MTRRPhysMask */
- movl $0x201, %ecx
+ movl $0x201, %ecx
/* This assumes we never access addresses above 2^36 in CAR. */
- movl $0x0000000f,%edx
- movl $(~(CacheSize-1)|0x800),%eax
+ movl $0x0000000f,%edx
+ movl $(~(CacheSize-1)|0x800),%eax
wrmsr
- /* enable write base caching so we can do execute in place
- * on the flash rom.
- */
+ /* enable write base caching so we can do execute in place
+ * on the flash rom.
+ */
/* MTRRPhysBase */
- movl $0x202, %ecx
- xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
+ movl $0x202, %ecx
+ xorl %edx, %edx
+ movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
/* MTRRPhysMask */
- movl $0x203, %ecx
- movl $0x0000000f,%edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $0x203, %ecx
+ movl $0x0000000f, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
-
- movl $MTRRdefType_MSR, %ecx
- xorl %edx, %edx
+ movl $MTRRdefType_MSR, %ecx
+ xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */
- movl $0x00000800, %eax
+ movl $0x00000800, %eax
wrmsr
- movl %cr0, %eax
- andl $0x9fffffff,%eax
- movl %eax, %cr0
+ movl %cr0, %eax
+ andl $0x9fffffff, %eax
+ movl %eax, %cr0
/* Read the range with lodsl*/
cld
- movl $CacheBase, %esi
- movl %esi, %edi
- movl $(CacheSize>>2), %ecx
- rep lodsl
+ movl $CacheBase, %esi
+ movl %esi, %edi
+ movl $(CacheSize>>2), %ecx
+ rep lodsl
- movl $CacheBase, %esi
- movl %esi, %edi
- movl $(CacheSize>>2), %ecx
+ movl $CacheBase, %esi
+ movl %esi, %edi
+ movl $(CacheSize >> 2), %ecx
/* 0x5c5c5c5c is a memory test pattern.
- * TODO: Check if everything works with the zero pattern as well. */
- /*xorl %eax, %eax*/
- xorl $0x5c5c5c5c,%eax
- rep stosl
+ * TODO: Check if everything works with the zero pattern as well. */
+ /*xorl %eax, %eax*/
+ xorl $0x5c5c5c5c,%eax
+ rep stosl
- movl CONFIG_XIP_ROM_BASE, %esi
- movl %esi, %edi
- movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
- rep lodsl
+ movl CONFIG_XIP_ROM_BASE, %esi
+ movl %esi, %edi
+ movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
+ rep lodsl
/* The key point of this CAR code is C7 cache does not turn into
* "no fill" mode, which is not compatible with general CAR code.
*/
- movl $(CacheBase+CacheSize-4), %eax
- movl %eax, %esp
+ movl $(CacheBase + CacheSize - 4), %eax
+ movl %eax, %esp
#ifdef CARTEST
testok: movb $0x40,%al
outb %al, $0x80
- xorl %edx, %edx
- xorl %eax, %eax
- movl $0x5c5c,%edx
+ xorl %edx, %edx
+ xorl %eax, %eax
+ movl $0x5c5c,%edx
pushl %edx
pushl %edx
pushl %edx
pushl %edx
pushl %edx
- popl %esi
- popl %esi
- popl %eax
- popl %eax
- popl %eax
+ popl %esi
+ popl %esi
+ popl %eax
+ popl %eax
+ popl %eax
cmpl %edx,%eax
jne stackerr
#endif
/* Restore the BIST result */
movl %ebp, %eax
+
/* We need to set ebp ? No need */
movl %esp, %ebp
- pushl %eax /* bist */
- call amd64_main
+ pushl %eax /* bist */
+ call amd64_main
/* We will not go back */
fixed_mtrr_msr: