diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-17 10:56:26 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-23 15:52:09 +0000 |
| commit | a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch) | |
| tree | 4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/cpu/via | |
| parent | 9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff) | |
| download | coreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz | |
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/via')
| -rw-r--r-- | src/cpu/via/nano/nano_init.c | 10 | ||||
| -rw-r--r-- | src/cpu/via/nano/update_ucode.c | 8 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 985a3c7303..cbd80cee72 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -71,7 +71,7 @@ static void nano_set_max_fid_vid(void) printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", cur_vid, min_vid, max_vid); - if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + if ((cur_fid != max_fid) || (cur_vid != max_vid)) { /* Set highest frequency and VID */ msr.lo = msr.hi; msr.hi = 0; @@ -101,7 +101,7 @@ static void nano_power(void) * This MSR is not documented by VIA docs, other than setting these * bits */ msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ( (1 << 7) | (1 << 4) ); + msr.lo |= ((1 << 7) | (1 << 4)); /* FIXME: Do we have a 6-bit or 7-bit VRM? * set bit [5] for 7-bit, or don't set it for 6 bit VRM * This will probably require a Kconfig option @@ -114,15 +114,15 @@ static void nano_power(void) /* Enable TM3 */ msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= ( (1 << 3) | (1 << 13) ); + msr.lo |= ((1 << 3) | (1 << 13)); wrmsr(IA32_MISC_ENABLE, msr); - u8 stepping = ( cpuid_eax(0x1) ) &0xf; + u8 stepping = (cpuid_eax(0x1)) & 0xf; if (stepping >= MODEL_NANO_3000_B0) { /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ + msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ msr.hi |= (1 << 0); /* C4e */ wrmsr(IA32_MISC_ENABLE, msr); } diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index b8bfd7da5a..efabac6224 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -43,9 +43,9 @@ static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) static void nano_print_ucode_info(const nano_ucode_header *ucode) { printk(BIOS_SPEW, "Microcode update information:\n"); - printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name); printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, - ucode->day, ucode->year ); + ucode->day, ucode->year); } static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) @@ -54,7 +54,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) if (ucode->signature != NANO_UCODE_SIGNATURE) return NANO_UCODE_SIGNATURE_ERROR; /* The size of the head must be exactly 12 double words */ - if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) return NANO_UCODE_WRONG_SIZE; /* How about a checksum ? Checksum must be 0 @@ -119,7 +119,7 @@ unsigned int nano_update_ucode(void) /* We might do a lot of loops searching for the microcode updates, but * keep in mind, nano_ucode_is_valid searches for the signature before * doing anything else. */ - for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + for (i = 0; i < (ucode_len >> 2); /* don't increment i here */) { ucode_update_status stat; const nano_ucode_header * ucode = (void *)(&ucode_data[i]); |