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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-30 21:22:40 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-30 21:22:40 +0000 |
| commit | 1d36d6df7dafea5a6f9dec80f4a3998470d440a2 (patch) | |
| tree | dd63064198bf6914420ab2b6c533d7578409d84c /src/cpu/via | |
| parent | 8463dd9db0dc2ce02423775d0eb62e28aa01e9f9 (diff) | |
| download | coreboot-1d36d6df7dafea5a6f9dec80f4a3998470d440a2.tar.xz | |
Use existing, readable MTRR #defines instead of hardcoding numbers.
Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
a little bit around (should not affect any functionality) to make the
Intel/AMD/VIA CAR implementations more similar and easier to compare.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/via')
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 40 |
1 files changed, 18 insertions, 22 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 4bbefef3cb..253c2143f0 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -78,36 +78,33 @@ var_mtrr_msr: .long 0x000 /* NULL, end of table */ clear_fixed_var_mtrr_out: - /* MTRRPhysBase */ - movl $0x200, %ecx + movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx movl $(CacheBase|MTRR_TYPE_WRBACK),%eax wrmsr - /* MTRRPhysMask */ - movl $0x201, %ecx + movl $MTRRphysMask_MSR(0), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f,%edx movl $(~(CacheSize-1)|0x800),%eax wrmsr - /* enable write base caching so we can do execute in place - * on the flash rom. - */ - /* MTRRPhysBase */ - movl $0x202, %ecx - xorl %edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + + /* enable write base caching so we can do execute in place + * on the flash rom. + */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr - /* MTRRPhysMask */ - movl $0x203, %ecx + movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr @@ -195,8 +192,7 @@ testok: /* Set the default memory type and disable fixed and enable variable MTRRs */ - movl $0x2ff, %ecx - //movl $MTRRdefType_MSR, %ecx + movl $MTRRdefType_MSR, %ecx xorl %edx, %edx /* Enable Variable and Disable Fixed MTRRs */ @@ -204,7 +200,7 @@ testok: wrmsr /* enable caching for first 1M using variable mtrr */ - movl $0x200, %ecx + movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx movl $(0 | 6), %eax //movl $(0 | MTRR_TYPE_WRBACK), %eax @@ -216,41 +212,41 @@ testok: * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. */ - movl $0x201, %ecx + movl $MTRRphysMask_MSR(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax wrmsr - movl $0x202, %ecx + movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx movl $(0x80000 | 6), %eax orl $(0 | 6), %eax wrmsr - movl $0x203, %ecx + movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax wrmsr - movl $0x204, %ecx + movl $MTRRphysBase_MSR(2), %ecx xorl %edx, %edx movl $(0xc0000 | 6), %eax orl $(0 | 6), %eax wrmsr - movl $0x205, %ecx + movl $MTRRphysMask_MSR(2), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax wrmsr /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ - movl $0x206, %ecx + movl $MTRRphysBase_MSR(3), %ecx xorl %edx, %edx movl $REAL_XIP_ROM_BASE,%eax orl $(0 | 6), %eax wrmsr - movl $0x207, %ecx + movl $MTRRphysMask_MSR(3), %ecx xorl %edx, %edx movl $CONFIG_XIP_ROM_SIZE,%eax decl %eax |