summaryrefslogtreecommitdiff
path: root/src/cpu/via
diff options
context:
space:
mode:
authorEric Biederman <ebiederm@xmission.com>2004-11-11 06:53:24 +0000
committerEric Biederman <ebiederm@xmission.com>2004-11-11 06:53:24 +0000
commit69afe2822a960c1d2b0c84854ea6a2cd1eec29f9 (patch)
tree6dab2d4aaa4bdeeffff440a6ea96817b70043bd3 /src/cpu/via
parent8d54bd4471267bd77f105c48f6c8e12449bd375e (diff)
downloadcoreboot-69afe2822a960c1d2b0c84854ea6a2cd1eec29f9.tar.xz
mpspec.h: Tweak the write_smp_table macro so that it is safe if passed a complex expression.
crt0.S.lb: Modified so that it is safe to include console.inc console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc socket_754/Config.lb Conditionally set config chip.h socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references. slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops slot_2/slot2.c: The same spelling fix socket_mPGA603/chip.h: again socket_mPGA603/socket_mPGA603_400Mhz.c: and again socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME socket_mPGA604_800Mhz/chip.h: Another spelling fix socket_mPGA604_800Mhz.c and again via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates earlymtrr.c: Remove work around for older versions of romcc pci_ids.h: More ids. malloc.c: We don't need string.h any longer uart8250.c: Be consistent when delcaring functions static inline arima/hdama/mptable.c: Cleanup to be a little more consistent amdk8/coherent_ht.c: - Talk about nodes not cpus (In preparation for dual cores) - Remove clear_temp_row (as it is no longer needed) - Demoted the failure messages to spew. - Modified to gracefully handle failure (It should work now if cpus are removed) - Handle the non-SMP case in verify_mp_capabilities - Add clear_dead_routes which replaces clear_temp_row and does more - Reorganize setup_coherent_ht_domain to cleanly handle failure. - incoherent_ht.c: Clean up the indenation a little. i8259.c: remove blank lines at the start of the file. keyboard.c: Make pc_keyboard_init static ramtest.c: Add a print out limiter, and cleanup the printout a little. amd8111/Config.lb: Mention amd8111_smbus.c amd8111_usb.c: Call the structure usb_ops not smbus_ops. NSC/pc97307/chip.h: Fix spelling issue pc97307/superio.c: Use &ops no &pnp_ops. w83627hf/suerio.c: ditto w83627thf/suerio.c: ditto buildrom.c: Use braces around the body of a for loop. It's more maintainable. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/via')
-rw-r--r--src/cpu/via/model_centaur/model_centaur_init.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/via/model_centaur/model_centaur_init.c b/src/cpu/via/model_centaur/model_centaur_init.c
index af2b7464b1..52e8ee44a6 100644
--- a/src/cpu/via/model_centaur/model_centaur_init.c
+++ b/src/cpu/via/model_centaur/model_centaur_init.c
@@ -11,28 +11,11 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
-static uint32_t microcode_updates[] = {
- /* WARNING - Intel has a new data structure that has variable length
- * microcode update lengths. They are encoded in int 8 and 9. A
- * dummy header of nulls must terminate the list.
- */
-
- /* Dummy terminator */
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0,
-};
-
-
static void model_centaur_init(device_t dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
x86_mtrr_check();
-
- /* Update the microcode */
- intel_update_microcode(microcode_updates);
/* Enable the local cpu apics */
setup_lapic();