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authorAaron Durbin <adurbin@chromium.org>2015-09-02 22:23:11 -0500
committerAaron Durbin <adurbin@chromium.org>2015-09-04 15:09:32 +0000
commit439356fabcacbbc3a3231f6e27b5298f8f5ad41f (patch)
tree82e94a01f5a59b1d495db0e6225556bbbd0edfb0 /src/cpu/via
parentbc98cc66b2fe787173ec04b84ea11bc3e57fe373 (diff)
downloadcoreboot-439356fabcacbbc3a3231f6e27b5298f8f5ad41f.tar.xz
x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/via')
-rw-r--r--src/cpu/via/c7/Makefile.inc2
-rw-r--r--src/cpu/via/nano/Makefile.inc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/via/c7/Makefile.inc b/src/cpu/via/c7/Makefile.inc
index 417d762751..8c13d91a92 100644
--- a/src/cpu/via/c7/Makefile.inc
+++ b/src/cpu/via/c7/Makefile.inc
@@ -7,4 +7,4 @@ subdirs-y += ../../intel/microcode
ramstage-y += c7_init.c
-cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
index b5d00ecb4a..d3df3fbcc0 100644
--- a/src/cpu/via/nano/Makefile.inc
+++ b/src/cpu/via/nano/Makefile.inc
@@ -30,4 +30,4 @@ ramstage-y += update_ucode.c
# the rest of coreboot.
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
-cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc