diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 19:15:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:28:27 +0200 |
| commit | 585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (patch) | |
| tree | 05b159c11a72cbd4bcbf18e67a639177388d78a0 /src/cpu/x86/16bit/entry16.inc | |
| parent | 9071670a84281979709191307dc11f1350f81bd8 (diff) | |
| download | coreboot-585d1a0e7d0025e459a35b470572bcdbfff4e3c8.tar.xz | |
src/cpu: Capitalize ROM and RAM
Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/x86/16bit/entry16.inc')
| -rw-r--r-- | src/cpu/x86/16bit/entry16.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index be5b73019e..a512227f29 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -95,7 +95,7 @@ _start16bit: * * Also load an IDT with NULL limit to prevent the 16bit IDT being used * in protected mode before c_start.S sets up a 32bit IDT when entering - * ram stage. In practise: CPU will shutdown on any exception. + * RAM stage. In practise: CPU will shutdown on any exception. * See IA32 manual Vol 3A 19.26 Interrupts. */ |