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| author | Martin Roth <martinroth@google.com> | 2015-11-12 14:02:42 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-19 00:16:50 +0100 |
| commit | 1455437c9e010bcc617c5927e18cf1cb3b02c82f (patch) | |
| tree | 090b6d94cdd166d4302aa0053c8d37cfb19de642 /src/cpu/x86/16bit | |
| parent | ae16c4034c37a28e352936d0600b51be21340524 (diff) | |
| download | coreboot-1455437c9e010bcc617c5927e18cf1cb3b02c82f.tar.xz | |
x86: Add Kconfig to disable early bootblock postcodes
The Intel cave creek chipset needs to have port 80 routing configured
before any post codes can be sent to port 80h. Sending post codes out
before the routing is done will hang the system.
This patch allows us to disable the first couple of post codes that go
out before the routing can be configured.
The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx).
Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12422
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
Diffstat (limited to 'src/cpu/x86/16bit')
| -rw-r--r-- | src/cpu/x86/16bit/entry16.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 4dad1e5a7b..abaf6718ea 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,8 +36,9 @@ _start: cli /* Save the BIST result */ movl %eax, %ebp - +#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_RESET_VECTOR_CORRECT) +#endif /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before * executing any further code. Even though paging is disabled we |