summaryrefslogtreecommitdiff
path: root/src/cpu/x86/16bit
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 18:58:27 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:33:06 +0200
commitd82be923b10ef18c64c9565e03959736589ef089 (patch)
tree6669d03179a5d67183fe50eb4a1d259195679e53 /src/cpu/x86/16bit
parent918535a657b4ee393708640aa2e8ed3c75de20b9 (diff)
downloadcoreboot-d82be923b10ef18c64c9565e03959736589ef089.tar.xz
src/cpu: Capitalize CPU
Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15934 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/x86/16bit')
-rw-r--r--src/cpu/x86/16bit/entry16.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index a512227f29..b4db83400d 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -54,7 +54,7 @@ _start16bit:
* If we are hyperthreaded or we have multiple cores it is bad,
* for SMP startup. On Opterons it causes a 5 second delay.
* Invalidating the cache was pure paranoia in any event.
- * If you cpu needs it you can write a cpu dependent version of
+ * If you CPU needs it you can write a CPU dependent version of
* entry16.inc.
*/