diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/cpu/x86/16bit | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/x86/16bit')
| -rw-r--r-- | src/cpu/x86/16bit/entry16.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2a9f8c55e9..9e00c55a92 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,8 @@ #include <arch/rom_segs.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \ - IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \ + CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ @@ -44,7 +44,7 @@ _start16bit: cli /* Save the BIST result */ movl %eax, %ebp -#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) +#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_RESET_VECTOR_CORRECT) #endif |