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| author | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 19:29:29 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 19:29:29 +0000 |
| commit | fcd5ace00b333ce31b11b02a2243dfbf39307f10 (patch) | |
| tree | d686d752ccea9b185b0008c70d8523749b26e2dd /src/cpu/x86/32bit/entry32.lds | |
| parent | 98e619b1cefcb9871185f4cc3db85fa430dcdbce (diff) | |
| download | coreboot-fcd5ace00b333ce31b11b02a2243dfbf39307f10.tar.xz | |
- Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/32bit/entry32.lds')
| -rw-r--r-- | src/cpu/x86/32bit/entry32.lds | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/x86/32bit/entry32.lds b/src/cpu/x86/32bit/entry32.lds new file mode 100644 index 0000000000..37a75ba6ae --- /dev/null +++ b/src/cpu/x86/32bit/entry32.lds @@ -0,0 +1,14 @@ +/* + _cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0; + _cache_ram_seg_base_low = (_cache_ram_seg_base) & 0xffff; + _cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff; + _cache_ram_seg_base_high = (_cache_ram_seg_base >> 24) & 0xff; + + _rom_code_seg_base = _ltext - _text; + _rom_code_seg_base_low = (_rom_code_seg_base) & 0xffff; + _rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff; + _rom_code_seg_base_high = (_rom_code_seg_base >> 24) & 0xff; +*/ + + + |