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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-12 17:32:09 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-02 16:15:19 +0000 |
| commit | 47be2d9f70c0112da29d560cbef13b6f2bcd5697 (patch) | |
| tree | 16a963e38dfaf42a96b6e9721d144722e1615b90 /src/cpu/x86/Kconfig | |
| parent | d60089b7b1f32271da109997c53f85dab6c03afd (diff) | |
| download | coreboot-47be2d9f70c0112da29d560cbef13b6f2bcd5697.tar.xz | |
cpu/x86: Add a prog_run hook to set up caching of XIP stages
Some platforms lack a non-eviction mode and therefore caching the
whole ROM to speed up XIP stages can be dangerous as it could result
in eviction if too much of the ROM is being accessed. The solution is
to only cache a region, about the size of the stage that the bootblock
is about to load: verstage and/or romstage.
TODO: now a limit of 256KiB is set for the total amount of cache that
can be used. This should fit most use cases for the time being.
Change-Id: I94d5771a57ffd74d53db3e35fe169d77d7fbb8cd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/x86/Kconfig')
| -rw-r--r-- | src/cpu/x86/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a8cf54d89e..b316c1ffc3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -78,6 +78,16 @@ config XIP_ROM_SIZE depends on !NO_FIXED_XIP_ROM_SIZE default 0x10000 +config SETUP_XIP_CACHE + bool + depends on C_ENVIRONMENT_BOOTBLOCK + depends on !NO_XIP_EARLY_STAGES + help + Select this option to set up an MTRR to cache XIP stages loaded + from the bootblock. This is useful on platforms lacking a + non-eviction mode and therefore need to be careful to avoid + eviction. + config CPU_ADDR_BITS int default 36 |