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authorAaron Durbin <adurbin@chromium.org>2014-02-25 20:36:56 -0600
committerAaron Durbin <adurbin@google.com>2014-03-07 15:30:27 +0100
commitc34713d33e088095acb6dd61527a26117d9c368e (patch)
tree020c5387801605f753fca25cc6b2c09ff5763e30 /src/cpu/x86/Makefile.inc
parent7274800ea37edf41cb50e899d03baa02bdeecade (diff)
downloadcoreboot-c34713d33e088095acb6dd61527a26117d9c368e.tar.xz
x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/x86/Makefile.inc')
-rw-r--r--src/cpu/x86/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index d5bc2fd219..277ba484a6 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -3,6 +3,7 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += car.c
subdirs-$(CONFIG_PARALLEL_MP) += name
ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
+ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c
SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf
SIPI_BIN=$(SIPI_ELF:.elf=)