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author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:17:25 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:17:25 +0000 |
commit | 6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch) | |
tree | cc45ae7c4dea6e2c5338f52b4314106bf07023be /src/cpu/x86/car/cache_as_ram_post.c | |
parent | b2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff) | |
download | coreboot-6ca7636c8f52560e732cdd5b1c7829cda5aa2bde.tar.xz |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/car/cache_as_ram_post.c')
-rw-r--r-- | src/cpu/x86/car/cache_as_ram_post.c | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/src/cpu/x86/car/cache_as_ram_post.c b/src/cpu/x86/car/cache_as_ram_post.c new file mode 100644 index 0000000000..8cbc1e9cba --- /dev/null +++ b/src/cpu/x86/car/cache_as_ram_post.c @@ -0,0 +1,82 @@ + + __asm__ volatile ( + /* + FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. + It is only needed if we want to go back + */ + + /* We don't need cache as ram for now on */ + /* disable cache */ + "movl %cr0, %eax\n\t" + "orl $(0x1<<30),%eax\n\t" + "movl %eax, %cr0\n\t" + + /* clear sth */ + "movl $0x200, %ecx\n\t" + "xorl %edx, %edx\n\t" + "xorl %eax, %eax\n\t" + "wrmsr\n\t" + "movl $0x201, %ecx\n\t" + "wrmsr\n\t" + + /* enable fast string operation */ + "movl $0x1a0, %ecx\n\t" + "rdmsr\n\t" + "orl $1, %eax\n\t" + "wrmsr\n\t" + +#if defined(CLEAR_FIRST_1M_RAM) + /* enable caching for first 1M using variable mtrr */ + "movl $0x200, %ecx\n\t" + "xorl %edx, %edx\n\t" + "movl $(0 | 1), %eax\n\t" +// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t" + "wrmsr\n\t" + + "movl $0x201, %ecx\n\t" + "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/ + "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t" + "wrmsr\n\t" +#endif + + /* enable cache */ + "movl %cr0, %eax\n\t" + "andl $0x9fffffff,%eax\n\t" + "movl %eax, %cr0\n\t" +#if defined(CLEAR_FIRST_1M_RAM) + /* clear the first 1M */ + "movl $0x0, %edi\n\t" + "cld\n\t" + "movl $(0x100000>>2), %ecx\n\t" + "xorl %eax, %eax\n\t" + "rep stosl\n\t" + + /* disable cache */ + "movl %cr0, %eax\n\t" + "orl $(0x1<<30),%eax\n\t" + "movl %eax, %cr0\n\t" + + /* enable caching for first 1M using variable mtrr */ + "movl $0x200, %ecx\n\t" + "xorl %edx, %edx\n\t" + "movl $(0 | 6), %eax\n\t" +// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t" + "wrmsr\n\t" + + "movl $0x201, %ecx\n\t" + "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/ + "movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t" + "wrmsr\n\t" + + /* enable cache */ + "movl %cr0, %eax\n\t" + "andl $0x9fffffff,%eax\n\t" + "movl %eax, %cr0\n\t" + "invd\n\t" + + /* + FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back + But the problem is the range is some io related, So don't go back + */ +#endif + ); |